LTC1291(RevA) 查看數據表（PDF） - Linear Technology

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LTC1291
(Rev.:RevA)

Single Chip 12-Bit Data Acquisition System

Linear Technology 

LTC1291

APPLICATI S I FOR ATIO

RC Input Filtering

It is possible to filter the inputs with an RC network as

shown in Figure 12. For large values of CF (e.g., 1µF) the

capacitive input switching currents are averaged into a net

DC current. A filter should be chosen with a small resistor

and a large capacitor to prevent DC drops across the

resistor. The magnitude of the DC current is approximately

IDC = 100pF • VIN/tCYC and is roughly proportional to VIN.

When running at the minimum cycle time of 18.5µs, the

input current equals 27µA at VIN = 5V. Here a filter resistor

of 4.5Ω will cause 0.1LSB of full-scale error. If a large filter

resistor must be used, errors can be reduced by increasing

the cycle time as shown in the Typical Performance

Characteristics curve Maximum Filter Resistor vs Cycle

Time.

RFILTER IDC

VIN –

“+”

CFILTER

LTC1291

“–”

LTC1291 F12

Figure 12. RC Input Filtering

Input Leakage Current

Input leakage currents also can create errors if the source

resistance gets too large. For example, the maximum input

leakage specification of 1µA (at 125°C) flowing through a

source resistance of 1k will cause a voltage drop of 1mV

or 0.8LSB. This error will be much reduced at lower

temperatures because leakage drops rapidly (see typical

performance characteristics curve Input Channel Leakage

Current vs Temperature).

SAMPLE-AND-HOLD

Single-Ended Input

The LTC1291 provides a built-in sample-and-hold (S/H)

function on the +IN input for signals acquired in the single-

ended mode (–IN pin grounded). The sample-and-hold

allows the LTC1291 to convert rapidly varying signals (see

typical performance characteristics curve of S/H Acquisition

Time vs Source Resistance). The input voltage is sampled

during the tSMPL time as shown in Figure 9. The sampling

interval begins as the bit preceding the MSBF bit is shifted

in and continues until the falling edge of the PS bit is

received. On this falling edge, the S/H goes into the hold

mode and the conversion begins.

Differential Input

With a differential input the A/D no longer converts a single

voltage but converts the difference between two voltages.

The voltage on the +IN pin is sampled and held and can be

rapidly time varying. The voltage on the –IN pin must

remain constant and be free of noise and ripple throughout

the conversion time. Otherwise the differencing operation

will not be done accurately. The conversion time is 12 CLK

cycles. Therefore a change in the –IN input voltage during

this interval can cause conversion errors. For a sinusoidal

voltage on the –IN input this error would be:

( ) VERROR(MAX) =

2π

f(−IN)VPEAK





12

fCLK





Where f(–IN) is the frequency of the –IN input voltage,

VPEAK is its peak amplitude and fCLK is the frequency of the

CLK. Usually VERROR will not be significant. For a 60Hz

signal on the –IN input to generate a 0.25LSB error

(300µV) with the converter running at CLK = 1MHz, its

peak value would have to be 66mV. Rearranging the above

equation, the maximum sinusoidal signal that can be

digitized to a given accuracy is given as:

f(−IN)

=





VERROR(MAX)

2πVPEAK 



f1CL2K

For 0.25LSB error (300µV), the maximum input sinusoid

with a 5V peak amplitude that can be digitized is 0.8Hz.

1291fa

17

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