LTC2246LX(RevB) 查看數據表（PDF） - Linear Technology

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LTC2246LX
(Rev.:RevB)

14-Bit, 25Msps 125°C ADC In LQFP

Linear Technology 

LTC2246H

APPLICATIONS INFORMATION

Driving the Clock Input

The CLK input can be driven directly with a CMOS or TTL

level signal. A differential clock can also be used along

with a low-jitter CMOS converter before the CLK pin (see

Figure 8).

The noise performance of the LTC2246H can depend on the

clock signal quality as much as on the analog input. Any

noise present on the clock signal will result in additional

aperture jitter that will be RMS summed with the inherent

ADC aperture jitter.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2246H is 25Msps.

For the ADC to operate properly, the CLK signal should

have a 50% (±5%) duty cycle. Each half cycle must have at

least 18.9ns for the ADC internal circuitry to have enough

settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the CLK pin to sample the analog

input. The falling edge of CLK is ignored and the internal

falling edge is generated by a phase-locked loop. The

input clock duty cycle can vary and the clock duty cycle

stabilizer will maintain a constant 50% internal duty cycle.

If the clock is turned off for a long period of time, the duty

cycle stabilizer circuit will require a hundred clock cycles

for the PLL to lock onto the input clock. To use the clock

duty cycle stabilizer, the MODE pin should be connected

to 1/3VDD or 2/3VDD using external resistors.

If the clock duty cycle stabilizer is used, a >1μs high pulse

should be applied to the SHDN pin once the power supplies

are stable at power up.

The lower limit of the LTC2246H sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating frequency

for the LTC2246H is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overflow bit.

14

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

D13 – D0

D13 – D0

(2V Range)

OF

(Offset Binary) (2’s Complement)

>+1.000000V

+0.999878V

+0.999756V

1 11 1111 1111 1111 01 1111 1111 1111

0 11 1111 1111 1111 01 1111 1111 1111

0 11 1111 1111 1110 01 1111 1111 1110

+0.000122V

0.000000V

–0.000122V

–0.000244V

0 10 0000 0000 0001 00 0000 0000 0001

0 10 0000 0000 0000 00 0000 0000 0000

0 01 1111 1111 1111 11 1111 1111 1111

0 01 1111 1111 1110 11 1111 1111 1110

–0.999878V

–1.000000V

<–1.000000V

0 00 0000 0000 0001 10 0000 0000 0001

0 00 0000 0000 0000 10 0000 0000 0000

1 00 0000 0000 0000 10 0000 0000 0000

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, isolated

from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50Ω to external

circuitry and may eliminate the need for external damping

resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2246H should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

LTC2246H

VDD

VDD

OVDD 0.5V

TO 3.6V

0.1μF

DATA

FROM

LATCH

PREDRIVER

LOGIC

OE

OVDD

43Ω

TYPICAL

DATA

OUTPUT

OGND

2246H F09

Figure 9. Digital Output Buffer

2246hfb

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