LTC2272(RevA) 查看數據表（PDF） - Linear Technology
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LTC2272 Datasheet PDF : 44 Pages
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LTC2273/LTC2272
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
LTC2273
LTC2272
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX UNITS
VDD
Analog Supply Voltage
l 3.135 3.3 3.465 3.135 3.3 3.465
V
PSHDN
OVDD
Shutdown Power
Output Supply Voltage
IVDD
IOVDD
Analog Supply Current
Output Supply Current
SHDN = VDD
5
5
mW
CMLOUT Directly-Coupled, 50Ω to OVDD (Note 7) l 1.2
CMLOUT Directly-Coupled, 100Ω Diff. (Note 7)
1.4
CMLOUT AC-Coupled (Note 7)
1.4
VDD 1.2
VDD 1.4
VDD 1.4
VDD
V
VDD
V
VDD
V
DC Input
l
233 370
300 340
mA
CMLOUT Directly-Coupled, 50Ω to OVDD
l
8
CMLOUT Directly-Coupled, 100Ω Diff.
16
CMLOUT AC-Coupled
16
8
mA
16
mA
16
mA
PDIS Power Dissipation
DC Input
l
1100 1221
990 1122 mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2273
LTC2272
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX UNITS
fS
tCONV
tL
tH
tAP
Sampling Frequency
Conversion Period
ENC Clock Low Time
ENC Clock High Time
Sample-and-Hold Aperture Delay
(Note 9)
(Note 7)
(Note 7)
l 20
80
20
65
MHz
1/fS
1/fS
s
l 4.06 6.25
25
5.03 7.69
25
ns
l 4.06 6.25
25
5.03 7.69
25
ns
0.7
0.7
ns
tBIT, UI Period of a Serial Bit
tCONV/20
tCONV/20
s
tJIT
Total Jitter of CMLOUT± (P-P)
BER = 1E–12 (Note 7) l
0.35
0.35
UI
tR, tF Differential Rise and Fall Time of
RTERM = 50Ω, CL = 2pF l 50
110
50
110
ps
CMLOUT± (20% to 80%)
(Note 7)
tSU
SYNC to ENC Clock Setup Time
tHD
ENC Clock to SYNC Hold Time
tCS
ENC Clock to SYNC Delay
(Note 7)
(Note 7)
(Note 7)
l2
l 2.5
l tHD
2
2.5
tCONV – tSU tHD
ns
ns
tCONV – tSU ns
LATP
LATSC
LATSD
Pipeline Latency
Latency from SYNC Active to COMMA Out
Latency from SYNC Release to DATA Out
9
9
Cycles
3
3
Cycles
2
2
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 105MHz differential ENC+/ENC– = 2VP-P sine
wave with 1.6V common mode, input range = 2.25VP-P with differential
drive (PGA = 0), unless otherwise specified.
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best fit straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, fSAMPLE = 80Msps (LTC2273) or 65Msps (LTC2272)
input range = 2.25VP-P with differential drive.
Note 9: Recommended operating conditions.
Note 10: The dynamic current of the switched capacitors analog inputs
can be large compared to the leakage current and will vary with the sample
rate.
Note 11: Leakage current will have higher transient current at power up.
Keep drive resistance at or below 1k.
22732fa
6
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