LTC3707-SYNC 查看數據表（PDF） - Linear Technology
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LTC3707-SYNC Datasheet PDF : 32 Pages
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LTC3707-SYNC
APPLICATIO S I FOR ATIO
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
CSS > (COUT )(VOUT) (10 – 4) (RSENSE)
The minimum recommended soft-start capacitor of
CSS = 0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The current comparators have a maximum sense voltage
of 75mV resulting in a maximum MOSFET current of
75mV/RSENSE. The maximum value of current limit gener-
ally occurs with the largest VIN at the highest ambient
temperature, conditions that cause the highest power
dissipation in the top MOSFET.
The IC includes current foldback to help further limit load
current when the output is shorted to ground. The foldback
circuit is active even when the overload shutdown latch
described above is overridden. If the output falls below
70% of its nominal output level, then the maximum sense
voltage is progressively lowered from 75mV to 25mV.
Under short-circuit conditions with very low duty cycles,
the controller will begin cycle skipping in order to limit the
short-circuit current. In this situation the bottom MOSFET
will be dissipating most of the power but less than in
normal operation. The short-circuit ripple current is deter-
mined by the minimum on-time tON(MIN) of the LTC3707-
SYNC (less than 200ns), the input voltage and inductor
value:
∆IL(SC) = tON(MIN) (VIN/L)
The resulting short-circuit current is:
ISC
=
25mV
RSENSE
+
1
2
∆IL(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if VOUT returns to a safe level,
normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu-
late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage controlled oscillator is ±50% around the center
frequency fO. A voltage applied to the PLLFLTR pin of 1.2V
corresponds to a frequency of approximately 220kHz. The
nominal operating frequency range of the PLL is 140kHz
to 310kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
3707sf
20
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