LTM2881(RevA) 查看數據表（PDF） - Linear Technology

零件编号

产品描述 (功能)

生产厂家

LTM2881
(Rev.:RevA)

Complete Isolated RS485/RS422 µModule Transceiver + Power

Linear Technology 

LTM2881

Applications Information

PCB Layout Considerations

The high integration of the LTM2881 makes PCB layout

very simple. However, to optimize its electrical isolation

characteristics, EMI, and thermal performance, some

layout considerations are necessary. The PCB layout in

Figure 15 shows a recommended configuration for a low

EMI RS485 application.

• Under heavily loaded conditions, VCC and GND current

can exceed 300mA. Use sufficient copper on the PCB to

ensure resistive losses do not cause the supply voltage

to drop below the minimum allowed level. Similarly,

size the VCC2 and GND2 conductors to support any

external load current. These heavy copper traces will

also help to reduce thermal stress and improve the

thermal conductivity.

• Input and Output decoupling is not required, since

these components are integrated within the package.

If an additional decoupling capacitor is used a value of

6.8µF to 22µF is recommended. The recommendation

for EMI sensitive applications is to include an additional

low ESL ceramic capacitor of 1µF to 4.7µF, placed close

to the power and ground terminals. Alternatively, use a

number of smaller value parallel capacitors to reduce

ESL and achieve the same net capacitance.

• Hot plugging the LTM2881 voltage supply without ad-

ditional protection may cause device damage. Refer to

Linear Technology Application Note 88, entitled “Ceramic

Capacitors Can Cause Overvoltage Transients” for a

detailed discussion of this problem. To protect against

hot plug transients use a 6.8µF tantalum as the additional

decoupling capacitor.

• Do not place copper on the PCB between the inner col-

umns of pads. This area must remain open to withstand

the rated isolation voltage. Slot the PCB in this area to

facilitate cleaning and ensure contamination does not

compromise the isolation voltage.

• The recommendation for non-EMI critical applications

is to use solid ground planes for GND and GND2 for

optimizing signal fidelity, thermal performance, and to

minimize RF emissions due to uncoupled PCB trace

conduction. The drawback of using ground planes,

where EMI is of concern, is the creation of a dipole

antenna structure, which can radiate differential voltages

formed between GND and GND2. If ground planes are

used, minimize their area, and use contiguous planes,

any openings or splits can increase RF emissions.

• For large ground planes a small capacitance (≤ 330pF)

from GND to GND2, either discrete or embedded within

the substrate, provides a low impedance current return

path for the module parasitic capacitance, minimizing

any high frequency differential voltages and substantially

reducing radiated emissions. Discrete capacitance is not

as effective due to parasitic ESL; in addition consider

voltage rating, leakage, and clearance for component

selection. Embedding the capacitance within the PCB

substrate provides a near ideal capacitor and eliminates

the other component selection issues, however the PCB

must be 4 layers and the use of a slot is not compatible.

Exercise care in applying either technique to insure the

voltage rating of the barrier is not compromised.

C1

VCC = VL

= ON

RO

A

RE

B

DE

Z

DI

Y

TE

GND

2881 F15

Figure 15. PCB Recommended Layout

2881fa

15

Share Link: