DJLXT971ALC.A4 查看數據表（PDF） - Intel

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DJLXT971ALC.A4

3.3V Dual-Speed Fast Ethernet PHY Transceiver

Intel 

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Table 8. LXT971A Pin Types and Modes

Modes

RXD 0-3

RXDV

Tx/Rx

CLKS

Output

RXER COL CRS

Output Output Output

TXD 0-3

Input

TXEN

Input

TXER

Input

HWReset

DL

DL

DH

DL

DL

DL

IPLD

IPLD IPLD

SFTPWRDN DL

DL

Active DL

DL

DL

IPLD

IPLD IPLD

HWPWRDN High Z High Z High Z High Z High Z High Z High Z High Z High Z

ISOLATE

HZ w/

IPLD

HZ w/

IPLD

HZ w/

IPLD

HZ w/

IPLD

HZ w/

IPLD

HZ w/

IPLD

IPLD

IPLD IPLD

SLEEP

DL

DL

DL

DL

DL

DL

IPLD

IPLD IPLD

1. A High Z (High impedance) or three-state determines when the device is drawing a current of less than

20 nA. A High Z with PLD (High impedance with pull-down) state determines when the device is drawing a

current of less than 20 µA.

2. DL = Driven Low (Logic 0), DH = Driven High (Logic 1), IPLD = Internal Pull-Down (Weak)

20

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

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