LZ0P3817 查看數據表（PDF） - Sharp Electronics
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LZ0P3817 Datasheet PDF : 16 Pages
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LZ0P3817
TIMING CHART
[Normal Mode]
HORIZONTAL PULSE TIMING
HD
776 780
012 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92
CLK
ADOUT Normal 645 650 655OBπππππππππππππππOB
(D0-D7)
Mirror
10 5 1OBπππππππππππππππOB
HD
74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170
CLK
Y ADOUT Normal
(D0-D7)
R Mirror
OBππππππππππππππ OB 1 5 10 15 20 25 30 35 40
OBππππππππππππππ OB655 650 645 640 635 630 625 620 615
• The rising edge of the HD pulse must be between two rising edges of CLK (0) and CLK (1).
• The falling edge of the HD pulse must be between two rising edges of CLK (78) and CLK (79).
A PHASE RELATIONS BETWEEN DIGITAL OUTPUT (ADOUT) AND CLOCK (CLK)
CLK
I N ∆t
SYMBOL MIN. TYP. MAX. UNIT
∆t
45
ns
ADOUT
(D0-D7)
M VD
I HD
VERTICAL PULSE TIMING
SDI, SCLK, LOAD
Forbidden Period
523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Normal
L ADOUT
492 493 OB OB OB
(D0-D7)
Mirror
2 1 OB OB OB
OB OB OB 1 2 3 4 5 6 7
OB OB OB 493 492 491 490 489 488 487
E • The rising edge and falling edge of the VD pulse must be in high period of the HD pulses.
RAGC
SERIAL DATA TIMING (SDI, SCLK, LOAD)
Fixed
Gain
Offset
Shutter
D0
PSDI
D10
D20
D30
D37
SCLK
LOAD
• Data in SDI are taken at the rising edge of SCLK.
• Clock frequency of SCLK should be less than 1/2 of that of CLK.
• Do not insert the SDI, SCLK and LOAD pulses between 28H* and 29H*. Refer to "VERTICAL PULSE TIMING".
• Refer to "SERIAL DATA INPUTS" for the contents of serial data from D0 to D37.
* It means ordinal number of the HD pulse.
8
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