M41T94(2003) 查看數據表（PDF） - STMicroelectronics
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M41T94 Datasheet PDF : 31 Pages
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M41T94
READ and WRITE Cycles
Address and data are shifted MSB first into the Se-
rial Data Input (SDI) and out of the Serial Data
Output (SDO). Any data transfer considers the first
bit to define whether a READ or WRITE will occur.
This is followed by seven bits defining the address
to be read or written. Data is transferred out of the
SDO for a READ operation and into the SDI for a
WRITE operation. The address is always the sec-
ond through the eighth bit written after the Enable
(E) pin goes low. If the first bit is a '1,' one or more
WRITE cycles will occur. If the first bit is a '0,' one
or more READ cycles will occur (see Figure 12
and Figure 13, page 15).
Data transfers can occur one byte at a time or in
multiple byte burst mode, during which the ad-
dress pointer will be automatically incremented.
For a single byte transfer, one byte is read or writ-
ten and then E is driven high. For a multiple byte
Figure 12. READ Mode Sequence
transfer all that is required is that E continue to re-
main low. Under this condition, the address pointer
will continue to increment as stated previously. In-
crementing will continue until the device is dese-
lected by taking E high. The address will wrap to
00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). Although the clock contin-
ues to maintain the correct time, this will prevent
updates of time and date during either a READ or
WRITE of these address locations by the user.
The update will resume either due to a deselect
condition or when the pointer increments to an
non-clock or RAM address (08h to 3Fh).
Note: This is true both in READ and WRITE mode.
E
01234 56 789
12 13 14 15 16 17
22
SCL
W/R BIT
7 BIT ADDRESS
SDI
SDO
7654 3 210
MSB
DATA OUT
(BYTE 1)
DATA OUT
(BYTE 2)
HIGH IMPEDANCE
76 54321076543210
MSB
MSB
AI04635
14/31
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