M41T94(2003) 查看數據表（PDF） - STMicroelectronics

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M41T94
(Rev.:2003)

512 Bit (64 bit x8) SERIAL RTC (SPI) SRAM

STMicroelectronics 

Figure 13. WRITE Mode Sequence

E

0 1 2 3 4 5 6 7 8 9 10

15

SCL

M41T94

W/R BIT

7 BIT ADDR

DATA BYTE

SDI

SDO

7654321076543210 7

MSB

MSB

HIGH IMPEDANCE

AI04636

Data Retention Mode

With valid VCC applied, the M41T94 can be ac-

cessed as described above with READ or WRITE

cycles. Should the supply voltage decay, the

M41T94 will automatically deselect, write protect-

ing itself when VCC falls between VPFD (max) and

VPFD (min) (see Figure 14, page 15). At this time,

the Reset pin (RST) is driven active and will re-

main active until VCC returns to nominal levels.

When VCC falls below the switch-over voltage

(VSO), power input is switched from the VCC pin to

the SNAPHAT battery (or external battery for

SO16) at this time, and the clock registers are

maintained from the attached battery supply. All

outputs become high impedance. On power up,

when VCC returns to a nominal value, write protec-

tion continues for tREC by internally inhibiting E.

The RST signal also remains active during this

time (see Figure 14, page 15). Before the next ac-

tive cycle, Chip Enable should be taken high for at

least tEHEL, then low.

For a further more detailed review of battery life-

time calculations, please see Application Note

AN1012.

Figure 14. Power Down/Up Mode AC Waveforms

VCC

VPFD (max)

VPFD (min)

VSO

tF

tR

tFB

tRB

tDR

tREC

INPUTS

RECOGNIZED

DON'T CARE

RECOGNIZED

RST

OUTPUTS

VALID

(PER CONTROL INPUT)

HIGH-Z

VALID

(PER CONTROL INPUT)

AI03687

15/31

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