M470L3224FT0-LB3 查看數據表（PDF） - Samsung
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M470L3224FT0-LB3 Datasheet PDF : 20 Pages
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128MB, 256MB SODIMM
AC Timming Parameters & Specifications
Parameter
Symbol
Row cycle time
tRC
Refresh row cycle time
tRFC
Row active time
tRAS
RAS to CAS delay
tRCD
Row precharge time
tRP
Row active to Row active delay
tRRD
Write recovery time
tWR
Last data in to Read command
tWTR
Col. address to Col. address delay
tCCD
Clock cycle time
CL=2.0
tCK
CL=2.5
Clock high level width
tCH
Clock low level width
tCL
DQS-out access time from CK/CK
tDQSCK
Output data access time from CK/CK
tAC
Data strobe edge to ouput data edge
tDQSQ
Read Preamble
tRPRE
Read Postamble
tRPST
CK to valid DQS-in
tDQSS
DQS-in setup time
tWPRES
DQS-in hold time
tWPRE
DQS falling edge to CK rising-setup time
tDSS
DQS falling edge from CK rising-hold time tDSH
DQS-in high level width
tDQSH
DQS-in low level width
tDQSL
DQS-in cycle time
tDSC
Address and Control Input setup time(fast)
tIS
Address and Control Input hold time(fast)
tIH
Address and Control Input setup time(slow) tIS
Address and Control Input hold time(slow)
tIH
Data-out high impedence time from CK/CK tHZ
Data-out low impedence time from CK/CK
tLZ
B3
(DDR333@CL=2.5))
Min
Max
60
72
42
70K
18
18
12
15
1
1
7.5
12
6
12
0.45
0.55
0.45
0.55
-0.6
+0.6
-0.7
+0.7
-
0.45
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.75
0.75
0.8
0.8
+0.7
-0.7
+0.7
A2
(DDR266@CL=2.0)
Min
Max
65
75
45
120K
20
20
15
15
1
1
7.5
12
7.5
12
0.45
0.55
0.45
0.55
-0.75
+0.75
-0.75
+0.75
-
0.5
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.9
0.9
1.0
1.0
+0.75
-0.75
+0.75
DDR SDRAM
B0
(DDR266@CL=2.5))
Min
Max
65
75
45
120K
20
20
15
15
1
1
10
12
7.5
12
0.45
0.55
0.45
0.55
-0.75
+0.75
-0.75
+0.75
-
0.5
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.9
0.9
1.0
1.0
+0.75
-0.75
+0.75
Unit Note
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
tCK
tCK
ns
ns
ns
12
tCK
tCK
tCK
ns
3
tCK
tCK
tCK
tCK
tCK
tCK
ns i,5.7~9
ns i,5.7~9
ns i, 6~9
ns i, 6~9
ns
1
ns
1
Rev. 1.2 March 2004
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