M48T58Y-70PC1FE 查看數據表（PDF） - STMicroelectronics

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M48T58Y-70PC1FE

5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM

STMicroelectronics 

Data retention mode

5

Data retention mode

M48T58, M48T58Y

Note:

With valid VCC applied, the M48T58/Y operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs

become high impedance, and all inputs are treated as “don't care.”

A power failure during a WRITE cycle may corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the

user can be assured the memory will be in a write protected state, provided the VCC fall time

is not less than tF. The M48T58/Y may respond to transient noise spikes on VCC that reach

into the deselect window during the time the device is sampling VCC. Therefore, decoupling

of the power supply lines is recommended.

When VCC drops below VSO, the control circuit switches power to the internal battery which

preserves data and powers the clock. The internal button cell will maintain data in the

M48T58/Y for an accumulated period of at least 7 years when VCC is less than VSO. As

system power returns and VCC rises above VSO, the battery is disconnected, and the power

supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min)

plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent

inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume

trec after VCC exceeds VPFD (max).

For more information on Battery Storage Life refer to the Application Note AN1012.

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