M48T512Y(2010) 查看數據表（PDF） - STMicroelectronics
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M48T512Y Datasheet PDF : 23 Pages
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Operating modes
M48T512Y, M48T512V
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48T512Y
-70
M48T512V
-85
Min
Max
Min
Max
tAVAV
WRITE cycle time
70
85
tAVWL
Address valid to WRITE enable low
0
0
tAVEL
Address valid to chip enable low
0
0
tWLWH
WRITE enable pulse width
50
60
tELEH
Chip enable low to chip enable high
55
65
tWHAX
WRITE enable high to address transition
5
5
tEHAX
Chip enable high to address transition
10
15
tDVWH
Input valid to WRITE enable high
30
35
tDVEH
Input valid to chip enable high
30
35
tWHDX
WRITE enable high to input transition
5
5
tEHDX
tWLQZ(2)(3)
Chip enable high to input transition
WRITE enable low to output Hi-Z
10
15
25
30
tAVWH
Address valid to write enable high
60
70
tAVEH
Address valid to chip enable high
60
70
tWHQX(2)(3) WRITE enable high to output transition
5
5
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.3
Note:
Data retention mode
With valid VCC applied, the M48T512Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting
itself when VCC falls between VPFD (max) and VPFD (min). All outputs become high
impedance and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the current addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
memory will be in a write protected state, provided the VCC fall time is not less than tF. The
M48T512Y/V may respond to transient noise spikes on VCC that cross into the deselect
window during the time the device is sampling VCC.Therefore, decoupling of the power
supply lines is recommended. When VCC drops below VSO, the control circuit switches
power to the internal battery, preserving data and powering the clock. The internal energy
source will maintain data in the M48T512Y/V for an accumulated period of at least 10 years
at room temperature. As system power rises above VSO, the battery is disconnected, and
the power supply is switched to external VCC. Write protection continues until VCC reaches
VPFD (min) plus tREC (min). Normal RAM operation can resume tREC after VCC exceeds
VPFD (max). Refer to Application Note (AN1012) on the ST website for more information on
battery life.
10/23
Doc ID 5747 Rev 6
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