M48T512Y(2010) 查看數據表（PDF） - STMicroelectronics

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M48T512Y
(Rev.:2010)

5.0 or 3.3 V, 4 Mbit (512 Kbit x 8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T512Y, M48T512V

Operating modes

2.2

WRITE mode

The M48T512Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)

are low state after the address inputs are stable.

The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE

is terminated by the earlier rising edge of W or E. The addresses must be held valid

throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or

tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in

must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G

should be kept high during WRITE cycles to avoid bus contention; although, if the output bus

has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W

falls.

Figure 5. WRITE AC waveforms, WRITE enable controlled

A0-A18

E

W

DQ0-DQ7

tAVEL

tAVAV

VALID

tAVWH

tWHAX

tAVWL

tWLWH

tWLQZ

tWHDX

DATA INPUT

tDVWH

tWHQX

AI02386

Figure 6. WRITE AC waveforms, chip enable controlled

tAVAV

A0-A18

VALID

tAVEL

tAVEH

tELEH

E

tAVWL

tEHAX

W

tEHDX

DQ0-DQ7

DATA INPUT

tDVEH

AI02387

Doc ID 5747 Rev 6

9/23

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