Operating modes
M48Z35AV
WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 6. Write enable controlled, write mode AC waveforms
A0-A14
E
W
DQ0-DQ7
tAVEL
tAVAV
VALID
tAVWH
tWHAX
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI00926
Figure 7. Chip enable controlled, write mode AC waveforms
A0-A14
E
W
DQ0-DQ7
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tEHAX
tEHDX
DATA INPUT
tDVEH
AI00927
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