M48Z35AV 查看數據表（PDF） - STMicroelectronics
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M48Z35AV Datasheet PDF : 24 Pages
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M48Z35AV
5.0V or 3.3V, 256Kbit (32Kbit x 8) ZEROPOWER® SRAM
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ READ cycle time equals WRITE cycle time
■ Battery low flag (BOK)
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltage:
(VPFD = Power-fail deselect voltage)
– M48Z35AV: 2.7V ≤ VPFD ≤ 3.0V
■ Self-contained battery in the CAPHAT™ DIP
package
■ Packaging includes a 28-lead SOIC and
SNAPHAT® top (to be ordered separately)
■ Pin and function compatible with JEDEC
standard 32Kbit x 8 SRAMs
■ SOIC package provides direct connection for a
SNAPHAT top which contains the battery
■ RoHS compliant
– Lead-free second level interconnect
28
1
PCDIP28 (PC)
Battery CAPHAT
SNAPHAT (SH)
battery
28
1
SOH28 (MH)
November 2007
Rev 6
1/24
www.st.com
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