M58BV016DB7T3F 查看數據表（PDF） - Micron Technology
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M58BV016DB7T3F Datasheet PDF : 70 Pages
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Bus operations
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
3.2.2
Valid Data Ready may be configured (by bit M8 of burst configuration register) to be valid
immediately at the valid clock edge or one data cycle before the valid clock edge.
Synchronous burst read will be suspended if Burst Address Advance, B, goes High, VIH.
If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid.
If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address
Advance, B, is at VIL the internal Burst Address counter is incremented at each Burst Clock
K valid edge.
The synchronous burst read timing diagrams and AC characteristics are described in the
AC and DC parameters section. See Figure 13, Figure 14, Figure 15 and Figure 16, and
Table 20.
Synchronous burst read suspend
During a synchronous burst read operation it is possible to suspend the operation, freeing
the data bus for other higher priority devices.
A valid synchronous burst read operation is suspended when both Output Enable and Burst
Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the
burst counter and the Output Enable going High, VIH, inhibits the data outputs. The
synchronous burst read operation can be resumed by setting Output Enable Low.
Table 6. Synchronous burst read bus operations(1)(2)
Bus operation
Step
E G GD RP K(3) L B
A0-A18
DQ0-DQ31
Synchronous
burst read
Address Latch
Read
Read Suspend
Read Resume
Burst Address
Advance
VIL VIH X VIH T VIL X Address input
VIL VIL VIH VIH T VIH VIL Data output
VIL VIH X VIH X VIH VIH
High-Z
VIL VIL VIH VIH T VIH VIL Data output
VIL VIH X VIH T VIH VIL
High-Z
Read Abort, E
Read Abort, RP
VIH X X VIH X X X
X X X VIL X X X
High-Z
High-Z
1. X = don't care, VIL or VIH.
2. M15 = 0, bit M15 is in the burst configuration register.
3. T = transition, see M6 in the burst configuration register for details on the active edge of K.
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