M7020R-083ZA1 查看數據表（PDF） - STMicroelectronics
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M7020R-083ZA1 Datasheet PDF : 150 Pages
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M7020R
Table 7. AC Timing Parameters with CLK2X
M7020R-050 M7020R-066 M7020R-083
Row Symbol
Unit
Min Max Min Max Min Max
Description(1)
1
fCLOCK
100
133
166 MHz CLK2X frequency
2
tCLK
10
7.5
ns CLK2X period
3
tCKHI
4.0
3.0
ns CLK2X high pulse(2)
4
tCKLO
4.0
3.0
ns CLK2X low pulse(2
5
tISCH
2.5
2.5
2.5
ns Input Setup Time to CLK2X rising edge.(2)
6
tIHCH
0.6
0.6
0.6
ns Input Hold Time to CLK2X rising edge.(2)
Cascaded Input Setup Time to CLK2X rising
7
tICSCH 4.2
4.2
4.2
ns edge.(2)
Cascaded Input Hold Time to CLK2X rising
8
tICHCH 0.6
0.6
0.6
ns edge.(2)
9
tCKHOV
9.5
8.5
Rising edge of CLK2X to LHO, FULO, BHO,
ns FULL valid.(3)
10 tCKHDV
10.0
9.0
ns Rising edge of CLK2X to DQ valid.(2)
11 tCKHDZ 1.2 9.5 1.2 9.5 1.2 9.5 ns Rising edge of CLK2X to DQ high-Z.(4)
12 tCKHSV
10.0
9.0
ns Rising edge of CLK2X to SRAM Bus valid.(2)
13 tCKHSHZ
7.0
6.5
Rising edge of CLK2X to SRAM Bus high-
ns Z.(2,4)
14 tCKHSLZ 7.5
7.0
Rising edge of CLK2X to SRAM Bus low-
ns Z.(2,4)
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VDD = 1.8V.
2. Values are based on 50% signal levels.
3. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 14).
4. These parameters are sampled and not 100% tested, and are based on an AC load of 5pF.
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