M95160-DFCS6(2014) 查看數據表（PDF） - STMicroelectronics

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M95160-DFCS6
(Rev.:2014)

16-Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

Instructions

M95160 M95160-W M95160-R M95160-DF

6.2

Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction

to the device.

As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select

(S) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

• Power-up

• WRDI instruction execution

• WRSR instruction completion

• WRITE instruction completion.

Figure 9. Write Disable (WRDI) sequence

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