MAX1271ACAI 查看數據表（PDF） - Maxim Integrated
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MAX1271ACAI Datasheet PDF : 20 Pages
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Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
TIMING CHARACTERISTICS
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK =
2.0MHz (MAX127_B); fCLK = 1.8MHz (MAX127_A); TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.)
(Figures 2, 5, 7, 10)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DIN to SCLK Setup
tDS
100
ns
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse-Width High
tDH
tDO
tDV
tTR
tCSS
tCSH
tCH
CLOAD = 100pF
CLOAD = 100pF
0
ns
20
170
ns
120
ns
100
ns
100
ns
0
ns
200
ns
SCLK Pulse-Width Low
SCLK Fall to SSTRB
CS to SSTRB Output Enable
CS to SSTRB Output Disable
tCL
200
tSSTRB CLOAD = 100pF
tSDV CLOAD = 100pF, external clock mode only
tSTR CLOAD = 100pF, external clock mode only
ns
200
ns
200
ns
200
ns
SSTRB Rise to SCLK Rise
tSCK Internal clock mode only (Note 4)
0
ns
Note 1: Accuracy specifications tested at VDD = +5.0V. Performance at power-supply tolerance limit is guaranteed by power-supply
rejection test.
Note 2: External reference: VREF = 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels. VIN = ±5V (MAX1270), VIN = ±4V (MAX1271).
Note 4: Guaranteed by design, not production tested.
Note 5: Use static external loads during conversion for specified accuracy.
Note 6: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges.
Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6).
Note 9: Not production tested. Provided for design guidance only.
6 _______________________________________________________________________________________
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