MAX1875-MAX1876 查看數據表（PDF） - Maxim Integrated

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MAX1875-MAX1876

Dual 180° Out-of-Phase PWM Step-Down Controllers with POR

Maxim Integrated 

Dual 180° Out-of-Phase PWM Step-

Down Controllers with POR

Pin Description

PIN

NAME

FUNCTION

Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop by connecting a series

1

COMP2 resistor (RCOMP2) and capacitor (CCOMP2A) to GND in parallel with a second compensation capacitor

(CCOMP2B) as shown in Figure 1.

Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive-divider between REG2’s output

2

FB2

and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V,

connect FB2 to a resistive voltage-divider from REF to REG2’s output. See the Setting the Output

Voltage section.

Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to

3

ILIM2

100mV if ILIM2 is connected to VL. Connect a resistor (RILIM2) from ILIM2 to GND to adjust the

REG2’s current-limit threshold (VITH2) from 50mV (RILIM2 = 100kΩ) to 300mV (RILIM2 = 600kΩ). See

the Setting the Valley Current Limit section.

Oscillator Frequency Set Input. The controller generates the clock signal by dividing down the

oscillator, so the switching frequency equals half the synchronization frequency (fSW = fOSC/2).

4

OSC

Connect a resistor from OSC to GND (ROSC) to set the switching frequency from 100kHz (ROSC =

60kΩ) to 600kHz (ROSC = 10kΩ). The controller still requires ROSC when an external clock is

connected to SYNC. When using SYNC, set ROSC for one half of the SYNC input.

5

V+

Input Supply Voltage. 4.75V to 23V.

6

REF

2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor.

7

GND

Analog Ground

8

CKO

Clock Output. Clock Output for external 2- or 4-phase synchronization (see the Clock Synchronization

(SYNC, CKO) section).

Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect

9

SYNC

SYNC to a 200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase

operation as a master controller. Connect SYNC to VL for 4-phase operation as a master controller

(see the Clock Synchronization (SYNC, CKO) section).

Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to

10

ILIM1

100mV if ILIM1 is connected to VL. Connect a resistor (RILIM1) from ILIM1 to GND to adjust REG1’s

current-limit threshold (VITH1) from 50mV (RILIM1 = 100kΩ) to 300mV (RILIM1 = 600kΩ). See the

Setting the Valley Current Limit section.

Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive-divider between REG1’s output

11

FB1

and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V,

connect FB1 to a resistive voltage-divider from REF and REG1’s output. See the Setting the Output

Voltage section.

Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop by connecting a series

12

COMP1 resistor (RCOMP1) and capacitor (CCOMP1A) to GND in parallel with a second compensation capacitor

(CCOMP1B) as shown in Figure 1.

Open-Drain Reset Output (MAX1876 only). RST is low when either output voltage is more than 10%

below its regulation point. After soft-start is completed and both outputs exceed 90% of their nominal

13

RST

output voltage (VFB_ > 0.9V), RST becomes high impedance after a 140ms delay and remains high

impedance as long as both outputs maintain regulation. Connect a resistor between RST and the

logic supply for logic-level voltages.

6 _______________________________________________________________________________________

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