MAX445 查看數據表（PDF） - Maxim Integrated
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MAX445 Datasheet PDF : 8 Pages
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Low-Cost, High-Resolution, 200MHz
Video CRT Driver
Table 1. Peaking Networks
(RL = 200Ω, RS = 100Ω)
CL (pF) L3 (nH) L1 (nH) L2 (nH) CB (pF) tR (ns)
2
0
20
60
0.4
1.7
4
0
40
120
0.8
1.9
6
20
60
180
1.1
2.1
8
50
80
240
1.5
2.3
10
75
100
300
2.0
2.7
12
100
120
360
2.2
3.0
Inductors L1, L2, and L3 should be air or ferrite-core
coils with self-resonant frequencies higher than
500MHz.
Thermal Environment
The MAX445 can dissipate a large amount of power
depending on speed and load-driving requirements. The
power-tab package provides a low thermal resistance
path from the chip to an external heatsink. Be sure the
board design provides sufficient heatsinking capacity for
the intended operating range. When mounting to a chas-
sis, it should be noted that the device tab is attached to
VEE (-10.5V). This tab should be electrically isolated from
ground through a thermally conductive insulator.
It is highly recommended that the external heatsink be
connected to ground, since an arc or electrostatic dis-
charge entering the heatsink may break down or
bypass the tab insulator and damage the device. Also,
the grounded heatsink to package tab capacitance will
help to bypass the VEE supply. Another option would
be to bypass the heatsink to ground with a 0.01µF
capacitor with no tab insulator. Inadvertently shorting
the package tab to ground for less than 10 seconds will
not cause component damage. Junction-to-case ther-
mal resistance is rated at 6°C/W for the power-tab DIP
package. Table 2 shows the relationship of output volt-
age and duty cycle to total power.
Table 2. Power Dissipation at VAA = 70V
and Load Resistor = 200Ω
Output Level
Relative to
Black (V)
Duty Cycle
(%)
IC Power
(W)
Load Power
(W)
Total
(W)
0
0
1.6
0
1.6
35
100
7.8
6.1
13.9
35
80
6.5
4.9
11.4
50
80
5.6
10.0
15.6
Circuit Layout and Bypassing
Due to the extremely high-speed performance of the
MAX445, layout design precautions are required to
realize the display driver’s full high-speed capability.
The precautions are as follows:
1) A printed circuit board with a good, unbroken, low-
inductance ground plane is required.
2) Place a decoupling capacitor (0.01µF ceramic) as
close to VCC as possible.
3) Pay close attention to the decoupling capacitors’
resonant frequency and keep leads short.
4) On the inputs and outputs, keep lead lengths short
to avoid unwanted parasitic feedback around the
display driver.
5) Solder the MAX445 directly to the printed circuit
board. Do not use sockets.
200
3.0
175
2.5
150
2.0
125
1.5
100
2
4
6
8
10
12
LOAD CAPACITANCE (pF)
1.0
2
4
6
8
10
12
LOAD CAPACITANCE (pF)
Figure 2. Typical Rise/Fall Time vs. Loading, with Peaking Network Optimized for Load Capacitance
6 _______________________________________________________________________________________
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