MAX9317 查看數據表（PDF） - Maxim Integrated
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MAX9317 Datasheet PDF : 10 Pages
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Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
CLK
VIHD
VIHD - VILD
CLK
tPLH
VILD
tPHL
Q_
VOH
VOD
Q_
VOL
80%
Q_ - Q_
DIFFERENTIAL
OUTPUT
WAVEFORM
80%
0V
(DIFFERENTIAL)
20%
20%
tR
tF
Figure 1. MAX9317 Timing Diagram
Detailed Description
The MAX9317 family of low-skew, 1-to-5 dual differen-
tial drivers are designed for clock or data distribution.
Two independent 1-to-5 splitters accept a differential
input signal and reproduce it on five separate differen-
tial LVDS outputs. The output drivers are guaranteed to
operate at frequencies up to 1.0GHz with the LVDS out-
put levels conforming to the EIA/TIA-644 standard.
The MAX9317/MAX9317A operate from a 2.375V to
2.625V power supply for use in 2.5V systems. The
MAX9317B/MAX9317C operate from a 3.0V to 3.6V
supply for 3.3V systems.
Differential LVPECL and LVDS Input
The MAX9317 family has two input differential pairs:
CLKA and CLKA, and CLKB and CLKB. Each differen-
tial input pair can be configured or terminated indepen-
dently. The inputs are designed to be driven by either
LVPECL or LVDS signals with a maximum differential
voltage of VCC or 3.0V, whichever is less.
The MAX9317A/MAX9317C reduce external component
count by having the input 50Ω termination resistors on
chip. Configure the MAX9317A/MAX9317C to receive
LVPECL signals by connecting VT_ to VCC - 2V (Figure
2(a)). Leaving the VT_ input floating configures the
CLK_
CLK_
LVPECL
DRIVER
RIN
50Ω
VT_
VCC -
2.0V
RIN
50Ω
MAX9317A
MAX9317C
(a) MAX9317A/MAX9317C CONFIGURED FOR LVPECL INPUT SIGNALS.
LVDS
DRIVER
CLK_
RIN
50Ω
VT_
RIN
50Ω
CLK_
MAX9317A
MAX9317C
(b) MAX9317A/MAX9317C CONFIGURED FOR LVDS INPUT SIGNALS.
Figure 2. MAX9317A/MAX9317C Input Terminations
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