MAX9317 查看數據表（PDF） - Maxim Integrated
零件编号
产品描述 (功能)
生产厂家
MAX9317 Datasheet PDF : 10 Pages
| |||
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
respective input with a differential 100Ω termination to
receive LVDS signals (Figure 2(b)).
The MAX9317/MAX9317B accept LVPECL if the inputs
are externally terminated with 50Ω resistors from CLKA
and CLKA or CLKB and CLKB to VCC - 2V. Alternatively,
if the inputs are differentially terminated with 100Ω, they
accept an LVDS input signal.
The LVDS input signal must adhere to the specifications
given in the Electrical Characteristics table. Note that the
signal must be at least 1.2V to be a valid logic HIGH.
Applications Information
Output Termination
Terminate the outputs with 100Ω across each differen-
tial pair (Q_ to Q_). Ensure that output currents do not
exceed the current limits as specified in the Absolute
Maximum Ratings table. Under all operating conditions,
observe the device’s total thermal limits.
Power-Supply Bypassing
Bypass each VCC pin to ground with high-frequency sur-
face-mount ceramic 0.1µF and 0.01µF capacitors in par-
allel and as close to the device as possible, with the
0.01µF capacitor closest to the device. Use multiple par-
allel vias to minimize parasitic inductance and reduce
power-supply bounce with high-current transients.
Circuit Board Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals. Use
50Ω traces for CLK_, CLK_, Q_, and Q_. Maintaining
integrity is accomplished in part by reducing signal
reflections and skew, and increasing common-mode
noise immunity by keeping the differential traces close
together.
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, and not using sharp corners or vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 1119
PROCESS: Bipolar
TOP VIEW
32 31 30 29 28 27 26 25
GND 1
N.C. (VTA) 2
CLKA 3
CLKA 4
N.C. (VTB) 5
CLKB 6
CLKB 7
GND 8
MAX9317
MAX9317A
MAX9317B
MAX9317C
24 QA3
23 QA3
22 QA4
21 QA4
20 QB0
19 QB0
18 QB1
17 QB1
9 10 11 12 13 14 15 16
Pin Configurations
TOP VIEW
32 31 30 29 28 27 26 25
GND 1
N.C. (VTA) 2
CLKA 3
CLKA 4
N.C. (VTB) 5
CLKB 6
CLKB 7
GND 8
MAX9317
MAX9317A
MAX9317B
MAX9317C
**EXPOSED PADDLE
24 QA3
23 QA3
22 QA4
21 QA4
20 QB0
19 QB0
18 QB1
17 QB1
9 10 11 12 13 14 15 16
TQFP (7mm x 7mm)
( ) MAX9317A/MAX9317C.
QFN-EP**
**EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE.
_______________________________________________________________________________________ 7
Share Link: 