MB90F523B 查看數據表（PDF） - Fujitsu

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MB90F523B

16-bit Proprietary Microcontroller

Fujitsu 

MB90520A/520B Series

• BLOCK DIAGRAM

X0, X1

X0A, X1A

RST

HST

Main clock

Sub-clock

P07

7

P00/INT0 to P06/INT6

P24/AIN0

P25/BIN0

P26/ZIN0/INT7

P20/IC00

P21/IC01

P22/IC10

P23/IC11

P32/OUT0

P33/OUT1

P34/OUT2

P35/OUT3

P31/CKOT

P30

P36/PG00

P37/PG01

P40/PG10

P41/PG11

P42/SIN0

P43/SOT0

P44/SCK0

P45/SIN1

P46/SOT1

P47/SCK1

8

P10/WI0 to P17/WI7

Other pins

MD0 to MD2, C,

VCC, VSS

F2MC-16LX

CPU

Clock controller*1

(Includes

timebase timer)

Port 0*2

7 DTP/

external

interrupt

circuit

Port 2

3

8/16-bit

up/down

counter/

timer 0, 1

16-bit

I/O timer 1

2 Input

capture 0

(ICU)

16-bit

freerun

timer 0

4

Output

compare

0

(OCU)

Clock

output

Port 3

2

8/16-bit

2

PPG

timer 0, 1

UART

(SCI)

SIO ch.1

Port 4*2

Port 1*2

8 Wakeup

interrupts

Ports 8, 9*3, A

24

LCD

controller/

driver

4

Port 7

16-bit

reload

timer 0

16-bit

reload

timer 1

16-bit

I/O timer 2

Output

compare 1

4

(OCU)

16-bit

freerun

timer 1

8

P80/SEG16 to P87/SEG23

8

P90/SEG24 to P97/SEG31

8 PA0/SEG08 to PA7/SEG15

8

SEG00 to SEG07

4

V0 to V3

4

P74/COM0 to P77/COM3

P70/TI0/OUT4

P71/TO0/OUT5

P72/TI1/OUT6

P73/TO1/OUT7

Port 6

8

8/10-bit

A/D

converter

8

P60/AN0 to P67/AN7

AVCC

AVSS

AVRH

AVRL

P27/ADTG

Port 2

Interrupt controller

Port 5

SIO ch.2

P50/SIN2/AIN1

P51/SOT2/BIN1

P52/SCK2/ZIN1

8-bit 2

D/A

converter

× 2 ch

RAM

ROM

P53/DA0

P54/DA1

DVCC

DVSS

*1 : The clock control circuit includes the watchdog timer and timebase timer low power consumption control

circuits.

*2 : Incorporates a pull-up register setting register. CMOS level input and output.

*3 : As this port shares pins with the LCD output, the port uses N-ch open-drain circuits.

20

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