MB91314A 查看數據表（PDF） - Fujitsu

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MB91314A

32-bit Microcontroller

Fujitsu 

MB91314A Series

■ RESTRICTIONS

1) Clock control block

Take the oscillation stabilization wait time during “L” level input to the INIT pin.

2) Bit Search Module

The bit search data register for 0-detection (BSD0), and bit search data register for 1-detection (BSD1), and

bit search data register for change point detection (BSDC) are only word-accessible.

3) I/O port

Ports are accessed only in bytes.

4) Low Power Consumption Mode

• To place the device in standby mode, use the synchronous standby mode (set with bit 8 (SYNCS bit) of the

timebase counter control register, TBCR) and be sure to use the following sequence:

(ldi #value_of_standby, r0)

(ldi #_STCR, r12)

stb r0, @r12 // set STOP/SLEEP bit

ldub @r12, r0 // Must read STCR

ldub @r12, r0 // after reading, go into standby mode

nop

// Must insert NOP *5

nop

nop

nop

nop

• Please do not do the following when the monitor debugger is used.

• Setting of the break point to the above-mentioned instruction row.

• Execution of the step for the above-mentioned instruction row.

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