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MB95F133NSPFV 查看數據表(PDF) - Fujitsu

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MB95F133NSPFV Datasheet PDF : 63 Pages
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MB95130M Series
BLOCK DIAGRAM
RST
X0,X1
PG2/(X1A)*
PG1/(X0A)*
P00/INT00 to P07/INT07
P10/U10
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P15, P16
P00/AN00 to P07/AN07
AVCC
AVSS
F2MC-8FX CPU
Reset control
ROM
Clock control
Watch counter
Watch prescaler
RAM
Interrupt control
Wild register
External interrupt
8/16-bit PPG
UART/SIO
16-bit PPG
8/10-bit
A/D converter
Port
LIN-UART
8/16-bit
compound timer
Port
(P00/PPG00)
(P01/PPG01)
(P02/SCK)
(P03/SOT)
(P04/SIN)
(P05/TO00)
(P06/TO01)
(P12/EC0)
PF0, PF1
Other pins
MOD, VCC, VSS, C
*: Single clock product is a general-purpose port, and dual clock product is a sub clock oscillation pin.
17

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