MBM29BS32LF-18 查看數據表（PDF） - Spansion Inc.

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MBM29BS32LF-18

BURST MODE FLASH MEMORY CMOS 32M (2M × 16) BIT

Spansion Inc. 

MBM29BS/BT32LF-18/25

s COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register. Some

commands require Bank Address (BA) input. When command sequences are input into a bank reading, the

commands have priority over the reading. “MBM29BS/BT32LF Command Definitions Table” in sDEVICE BUS

OPERATIONS shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase

Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover, Read/Reset

commands are functionally equivalent, resetting the device to the read mode. Please note that commands are

always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.

Asynchronous Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, verify mode

of secter protect commands the Reset operation is initiated by writing the Reset command sequence into the

command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled

for reads until the command register contents are altered.

The device will automatically power-up in the Asynchronous Read/Reset state. In this case, a command

sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. While AVD

= VIL, asynchronous read operation is same as conventional Fujitsu Flash memory. Addresses are latched by

the rising edge of AVD or address change timing. tACC defined from address change timing or AVD falling edge,

because addresses are input to internal circuit while AVD = VIL. If the device is used by AVD ratch asynchronous

read operation, addresses should be kept from AVD falling edge to AVD rising edge or tACC defined by address

change timing, not AVD falling edge. This default value ensures that no spurious alteration of the memory content

occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing

parameters.

Synchronous (Burst) Read Command

This operation is enable after configuratrion register command is issued (A19 = 0). Addresses are latched by the

AVD rising edge or CLK active edge while AVD = VIL.

Configuration Register Set Command

The device uses a configuration register to set the various burst parameters: number of wait states, burst read

mode(burst length), active clock edge, RDY configuration, and synchronous Read mode active. The configuration

register must be set before the device will enter burst mode.

The configuration register is loaded with a three-cycle command sequence. The first two cycles are standard

unlock sequences. On the third cycle, the data should be C0h, address bits A11 to A0 should be 555h, address

bits A19 to A12 set the code to be latched, and address bit A20 is Don’t care. The device will power up or after a

hardware reset with the default setting, which is in asynchronous mode. The register must be set before the

device can enter synchronous mode. The configuration register can not be changed during device operations

(program, erase, or sector lock).

Read Mode Setting

On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the

system to enable or disable burst mode during system operations. Address A19 determines this setting: "1’ for

asynchronous mode, "0" for synchronous mode.

Programmable Wait State Configuration Setting

The programmable wait state feature informs the device of the number of clock cycles that must elapse after

AVD is driven active before data will be available. This value is determined by the input frequency of the device.

Address bits A14 to A12 determine the setting (see “Third Cycle Address/Data Table”).The wait state command

sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The

number of wait states that should be programmed into the device is directly related to the clock frequency.

20

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