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MC68060RC50

M68060 User’s Manual

Freescale Semiconductor 

3.1

3.2

3.2.1

3.2.1.1

3.2.1.2

3.2.1.3

3.2.1.4

3.2.1.5

3.2.2

3.2.2.1

3.2.2.2

3.2.2.3

3.2.2.4

3.2.2.5

4.1

4.1.1

4.1.2

4.1.3

4.2

4.2.1

4.2.2

4.2.2.1

4.2.2.2

4.2.2.3

4.2.3

4.2.4

4.2.4.1

4.2.4.2

4.2.4.3

4.2.4.4

4.2.5

4.2.6

4.2.6.1

4.2.6.2

4.2.6.3

4.3

4.4

4.5

4.6

4.6.1

Table of Contents

Section 3

Integer Unit

Integer Unit Execution Pipelines ................................................................... 3-1

Integer Unit Register Description .................................................................. 3-2

Integer Unit User Programming Model ....................................................... 3-2

Data Registers (D7–D0) ........................................................................... 3-2

Address Registers (A6–A0) ...................................................................... 3-2

User Stack Pointer (A7) ............................................................................ 3-2

Program Counter ...................................................................................... 3-3

Condition Code Register .......................................................................... 3-3

Integer Unit Supervisor Programming Model.............................................. 3-3

Supervisor Stack Pointer .......................................................................... 3-4

Status Register ......................................................................................... 3-4

Vector Base Register................................................................................ 3-4

Alternate Function Code Registers........................................................... 3-5

Processor Configuration Register............................................................. 3-5

Section 4

Memory Management Unit

Memory Management Programming Model.................................................. 4-3

User and Supervisor Root Pointer Registers .............................................. 4-3

Translation Control Register ....................................................................... 4-4

Transparent Translation Registers ............................................................. 4-6

Logical Address Translation.......................................................................... 4-7

Translation Tables ...................................................................................... 4-7

Descriptors................................................................................................ 4-12

Table Descriptors.................................................................................... 4-12

Page Descriptors .................................................................................... 4-12

Descriptor Field Definitions..................................................................... 4-13

Translation Table Example ....................................................................... 4-15

Variations in Translation Table Structure.................................................. 4-16

Indirect Action ......................................................................................... 4-16

Table Sharing Between Tasks................................................................ 4-17

Table Paging .......................................................................................... 4-17

Dynamically Allocated Tables................................................................. 4-17

Table Search Accesses ............................................................................ 4-19

Address Translation Protection................................................................. 4-20

Supervisor and User Translation Tables ................................................ 4-21

Supervisor Only ...................................................................................... 4-22

Write Protect ........................................................................................... 4-22

Address Translation Caches....................................................................... 4-24

Transparent Translation.............................................................................. 4-27

Address Translation Summary.................................................................... 4-28

RSTI and MDIS Effect on the MMU ............................................................ 4-28

Effect of RSTI on the MMUs ..................................................................... 4-28

MOTOROLA

M68060 USER’S MANUAL

xi

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