MCF51JF128 查看數據表（PDF） - Freescale Semiconductor

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MCF51JF128

Embedded - Microcontrollers

Freescale Semiconductor 

5.3.1 General Switching Specifications

Nonswitching electrical specifications

These general purpose specifications apply to all signals configured for EGPIO, MTIM,

CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V,

and full temperature range. The GPIO are set for high drive, no slew rate control, and no

input filter, digital or analog, unless otherwise specified.

Table 9. EGPIO General Control Timing

Symbol

Description

G1

Bus clock from CLK_OUT pin high to GPIO output valid

G2

Bus clock from CLK_OUT pin high to GPIO output invalid

(output hold)

G3

GPIO input valid to bus clock high

G4

Bus clock from CLK_OUT pin high to GPIO input invalid

GPIO pin interrupt pulse width (digital glitch filter disabled)

Synchronous path1

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter enabled)

Asynchronous path2

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter disabled)

Asynchronous path2

External reset pulse width (digital glitch filter disabled)

Mode select (MS) hold time after reset deassertion

Min.

—

1

28

—

1.5

100

50

100

2

Max.

32

—

—

4

—

—

—

—

—

Unit

ns

ns

ns

ns

Bus

clock

cycles

ns

ns

ns

Bus

clock

cycles

1. The greater synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.

Bus clock

Data outputs

Data inputs

G1

G2

G3

G4

Figure 3. EGPIO timing diagram

MCF51JF128 Data Sheet, Rev. 6, 01/2012.

Freescale Semiconductor, Inc.

19

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