Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin
Group
Primary
Function
Secondary
Function
Tertiary
Function
Quaternary
Function
Drive
Strength /
Control1
Slew Rate /
Control1
Pull-up /
Pull-down2
Pin on
100 LQFP
Pin on 81 Pin on 64
MAPBGA LQFP/QFN
UART 1
UCTS1
SYNCA
URXD2
GPIO PDSR[15] PSRR[15]
—
98
C3
61
URTS1
SYNCB
UTXD2
GPIO PDSR[14] PSRR[14]
—
4
B1
2
URXD1
—
—
GPIO PDSR[13] PSRR[13]
—
100
B2
63
UTXD1
—
—
GPIO PDSR[12] PSRR[12]
—
99
A2
62
UART 2
UCTS2
—
—
GPIO PDSR[27] PSRR[27]
—
27
—
—
URTS2
—
—
GPIO PDSR[26] PSRR[26]
—
30
—
—
URXD2
—
—
GPIO PDSR[25] PSRR[25]
—
28
—
—
UTXD2
—
FlexCAN CANRX4,11
CANTX4,11
—
GPIO PDSR[24] PSRR[24]
—
29
—
—
N/A
N/A
—
—
—
—
N/A
N/A
—
—
—
—
VSTBY
VSTBY
—
—
—
N/A
N/A
—
55
F8
37
VDD
VDD
—
—
—
N/A
N/A
—
1,2,14,22, D5,E3–E7, 1,10,20,39,5
23,34,41,
F5
2
57,68,81,93
VSS
VSS
—
—
—
N/A
N/A
—
3,15,24,25,3 A1,A9,D4,D 11,21,38,
5,42,56, 6,F4,F6,J1 53,64
67,75,82,92
1 The PDSR and PSSR registers are described in the General Purpose I/O chapter. All programmable signals default to 2 mA drive and FAST slew rate in
normal (single-chip) mode.
2 All signals have a pull-up in GPIO mode.
3 These signals are multiplexed on other pins.
4 The multiplexed CANTX and CANRX signals are not available on the MCF5211 or MCF5212.
5 For primary and GPIO functions only.
6 Only when JTAG mode is enabled.
7 CLKMOD0 and CLKMOD1 have internal pull-down resistors; however, the use of external resistors is very strongly recommended.
8 For secondary and GPIO functions only.
9 RSTI has an internal pull-up resistor; however, the use of an external resistor is very strongly recommended.
10 For GPIO function. Primary Function has pull-up control within the GPT module.
11 CANTX and CANRX are secondary functions only.