Electrical Specifications
BCLK
D1
data (write)
D2
BCLKE, SDXDQM, SDWE,
SDCS0, SDRAS, SDCAS
D3
A[24:9]
D4
data (read)
D5
Figure 3. SDRAM Bus Timing Diagram
Table 11. SDRAM Bus Timing Parameters
Timing to 50% Points
Maximum
ID
Characteristic
Units
30 pF 40 pF 50 pF
Load Load Load
D1 Propagation delay BCLK rising to data valid
7.88 8.8
9.6
ns
D2 Propagation delay BCLK rising to BCLKE, SDLDQM, 8.7
–
SDUDQM, SDWE, SDCS0, SDRAS, SDCAS valid
–
ns
D3 Propagation delay BCLK rising to A[24:9] valid
8.3 9.2
–
ns
D4 Set-up time data valid to BCLK rising
0
0
0
ns
D5 Hold time BCLK rising to data valid
0.7 0.7
0.7
ns
4.2 SPDIF Timing
The Sony/Philips Digital Interface (SPDIF) timing parameters are provided in Table 12. SPDIF timing is
totally asynchronous, therefore there is no need for relationship with the clock. Table 12 shows the
differences between high-low and low-high propagation delay which is called the skew.
MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 2.1
Freescale Semiconductor
15