Signal Descriptions
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1 Alternate 2 Dir.1
MCF5270
MCF5271
160 QFP
MCF5270
MCF5271
196 MAPBGA
CLKOUT
—
—
—
O
89
K14
Mode Selection
CLKMOD[1:0]
—
RCON
—
—
—
I
20,21
—
—
I
79
G5,H5
K10
External Memory Interface and Ports
A[23:21] PADDR[7:5] CS[6:4]
—
O 126, 125, 124 B11, C11, D11
A[20:0]
—
—
—
O
123:115, A12, B12, C12,
112:106, 102:98 A13, B13, B14,
C13, C14, D12,
D13, D14, E11,
E12, E13, E14,
F12, F13, F14,
G11, G12, G13
D[31:16]
—
—
—
O 22:30, 33:39 G1, G2, H1, H2,
H3, H4, J1, J2,
J3, J4, K1, K2,
K3, K4, L1, L2
D[15:8] PDATAH[7:0]
—
—
O
42:49
M1, N1, M2, N2,
P2, L3, M3, N3
D[7:0] PDATAL[7:0]
—
—
O 50:52, 56:60 P3, M4, N4, P4,
L5, M5, N5, P5
BS[3:0]
PBS[7:4] CAS[3:0]
—
O
143:140
B6, C6, D7, C7
OE
PBUSCTL7
—
—
O
62
N6
TA
PBUSCTL6
—
—
I
96
H11
TEA
PBUSCTL5 DREQ1
—
I
—
J14
R/W
PBUSCTL4
—
—
O
95
J13
TSIZ1
PBUSCTL3 DACK1
—
O
—
P6
TSIZ0
PBUSCTL2 DACK0
—
O
—
P7
TS
PBUSCTL1 DACK2
—
O
97
H13
TIP
PBUSCTL0 DREQ0
—
O
—
H12
Chip Selects
CS[7:4]
CS[3:2]
CS1
CS0
PCS[7:4]
—
—
PCS[3:2] SD_CS[1:0]
—
PCS1
—
—
—
—
—
O
—
B9, A10, C10,
A11
O
132,131
A9, C9
O
130
B10
O
129
D10
SDRAM Controller
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
Freescale Semiconductor
13