MCP23017 查看數據表（PDF） - Microchip Technology
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MCP23017 Datasheet PDF : 42 Pages
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MCP23017/MCP23S17
3.5 Configuration and Control
Registers
There are 21 registers associated with the MCP23X17,
as shown in Tables 3-4 and3-5. The two tables show
the register mapping with the two BANK bit values. Ten
registers are associated with PORTA and ten are
associated with PORTB. One register (IOCON) is
shared between the two ports. The PORTA registers
are identical to the PORTB registers, therefore, they
will be referred to without differentiating between the
port designation (i.e., they will not have the “A” or “B”
designator assigned) in the register tables.
TABLE 3-4: CONTROL REGISTER SUMMARY (IOCON.BANK = 1)
Register Address
Name
(hex)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
IODIRA
IPOLA
GPINTENA
DEFVALA
INTCONA
IOCON
GPPUA
INTFA
INTCAPA
GPIOA
OLATA
IODIRB
IPOLB
GPINTENB
DEFVALB
INTCONB
IOCON
GPPUB
INTFB
INTCAPB
GPIOB
OLATB
00
IO7
IO6
IO5
IO4
IO3
IO2
01
IP7
IP6
IP5
IP4
IP3
IP2
02
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2
03
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
04
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
05
BANK MIRROR SEQOP DISSLW HAEN
ODR
06
PU7
PU6
PU5
PU4
PU3
PU2
07
INT7
INT6
INT5
INT4
INT3
INT2
08
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
09
GP7
GP6
GP5
GP4
GP3
GP2
0A
OL7
OL6
OL5
OL4
OL3
OL2
10
IO7
IO6
IO5
IO4
IO3
IO2
11
IP7
IP6
IP5
IP4
IP3
IP2
12
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2
13
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
14
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
15
BANK MIRROR SEQOP DISSLW HAEN
ODR
16
PU7
PU6
PU5
PU4
PU3
PU2
17
INT7
INT6
INT5
INT4
INT3
INT2
18
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
19
GP7
GP6
GP5
GP4
GP3
GP2
1A
OL7
OL6
OL5
OL4
OL3
OL2
bit 1
IO1
IP1
GPINT1
DEF1
IOC1
INTPOL
PU1
INT1
ICP1
GP1
OL1
IO1
IP1
GPINT1
DEF1
IOC1
INTPOL
PU1
INT1
ICP1
GP1
OL1
bit 0
POR/RST
value
IO0 1111 1111
IP0 0000 0000
GPINT0 0000 0000
DEF0 0000 0000
IOC0 0000 0000
— 0000 0000
PU0 0000 0000
INTO 0000 0000
ICP0 0000 0000
GP0 0000 0000
OL0 0000 0000
IO0 1111 1111
IP0 0000 0000
GPINT0 0000 0000
DEF0 0000 0000
IOC0 0000 0000
— 0000 0000
PU0 0000 0000
INTO 0000 0000
ICP0 0000 0000
GP0 0000 0000
OL0 0000 0000
TABLE 3-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 0)
Register Address
Name
(hex)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
IODIRA
IODIRB
IPOLA
IPOLB
GPINTENA
GPINTENB
DEFVALA
DEFVALB
INTCONA
INTCONB
IOCON
IOCON
GPPUA
GPPUB
00
IO7
IO6
IO5
IO4
IO3
IO2
01
IO7
IO6
IO5
IO4
IO3
IO2
02
IP7
IP6
IP5
IP4
IP3
IP2
03
IP7
IP6
IP5
IP4
IP3
IP2
04
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2
05
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2
06
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
07
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
08
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
09
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
0A
BANK MIRROR SEQOP DISSLW HAEN
ODR
0B
BANK MIRROR SEQOP DISSLW HAEN
ODR
0C
PU7
PU6
PU5
PU4
PU3
PU2
0D
PU7
PU6
PU5
PU4
PU3
PU2
bit 1
IO1
IO1
IP1
IP1
GPINT1
GPINT1
DEF1
DEF1
IOC1
IOC1
INTPOL
INTPOL
PU1
PU1
bit 0
POR/RST
value
IO0 1111 1111
IO0 1111 1111
IP0 0000 0000
IP0 0000 0000
GPINT0 0000 0000
GPINT0 0000 0000
DEF0 0000 0000
DEF0 0000 0000
IOC0 0000 0000
IOC0 0000 0000
— 0000 0000
— 0000 0000
PU0 0000 0000
PU0 0000 0000
2005-2016 Microchip Technology Inc.
DS20001952C-page 17
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