MD80C88-2/B 查看數據表（PDF） - Intersil

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MD80C88-2/B

CMOS 8/16-Bit Microprocessor

Intersil 

80C88

Waveforms (Continued)

ANY

CLK

CYCLE

> 0-CLK

CYCLES

CLK

TCLGH

RQ/GT

(44)

(1)

TCLCL

PREVIOUS GRANT

AD7-AD0

80C88

TGVCH (14) TCLGL

TCHGX (15) (43) PULSE 2

80C88 GT

PULSE 1

COPROCESSOR

RQ

TCLGH (44)

TCLAZ (25)

PULSE 3

COPROCESSOR

RELEASE

COPROCESSOR

RD, LOCK

A19/S6-A16/S3

S2, S1, S0

TCHSZ (26)

TCHSV (21)

(SEE NOTE)

FIGURE 26. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.

CLK

HOLD

HLDA

A15-A8

AD7-AD0

A19/S6-A16/S3

RD, WR, I/O/M, DT/R, DEN, SSO

≥ 1CLK

CYCLE

1 OR 2

CYCLES

THVCH (13)

80C88

THVCH (13)

(SEE NOTE)

TCLHAV (36)

TCLAZ (19)

COPROCESSOR

TCHSZ (20)

TCLHAV (36)

80C88

TCHSV (21)

FIGURE 27. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

CLK

(13)

NMI

TINVCH (SEE NOTE)

INTR SIGNAL

TEST

FIGURE 28. ASYNCHRONOUS SIGNAL RECOGNITION

NOTE: Setup requirements for asynchronous signals only to guar-

antee recognition at next CLK.

CLK

ANY CLK CYCLE

TCLAV

(23)

ANY CLK CYCLE

TCLAV

(23)

LOCK

FIGURE 29. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

3-24

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