MFRC523 查看數據表（PDF） - NXP Semiconductors.

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MFRC523

Contactless Reader IC

NXP Semiconductors. 

NXP Semiconductors

27. Figures

Fig 1. Simplified block diagram of the MFRC523. . . . . . .4

Fig 2. Detailed block diagram of the MFRC523 . . . . . . . .5

Fig 3. Pinning configuration HVQFN32 (SOT617-1) . . . .6

Fig 4. MFRC523 Read/Write mode . . . . . . . . . . . . . . . . .8

Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode

communication diagram. . . . . . . . . . . . . . . . . . . . .8

Fig 6. Data coding and framing according to

ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 7. SPI connection to host . . . . . . . . . . . . . . . . . . . . .10

Fig 8. UART connection to microcontrollers . . . . . . . . . 11

Fig 9. UART read data timing diagram . . . . . . . . . . . . .14

Fig 10. UART write data timing diagram . . . . . . . . . . . . .15

Fig 11. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 12. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .17

Fig 13. START and STOP conditions . . . . . . . . . . . . . . .17

Fig 14. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .18

Fig 15. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .18

Fig 16. First byte following the START procedure . . . . . .19

Fig 17. Register read and write access . . . . . . . . . . . . . .20

Fig 18. I2C-bus HS mode protocol switch . . . . . . . . . . . .21

Fig 19. I2C-bus HS mode protocol frame. . . . . . . . . . . . .22

Fig 20. Serial data switch for TX1 and TX2 . . . . . . . . . . .26

Fig 21. Overview of MFIN and MFOUT signal routing . . .27

Fig 22. Quartz crystal connection . . . . . . . . . . . . . . . . . .32

Fig 23. Oscillator start-up time . . . . . . . . . . . . . . . . . . . . .33

Fig 24. Pin RX input voltage range . . . . . . . . . . . . . . . . .77

Fig 25. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . .78

Fig 26. Timing for Fast and Standard mode

devices on the I2C-bus. . . . . . . . . . . . . . . . . . . . .78

Fig 27. Typical application diagram . . . . . . . . . . . . . . . . .79

Fig 28. Output test signals TestDAC1 on pin AUX1

and TestDAC2 on pin AUX2 . . . . . . . . . . . . . . . .82

Fig 29. Output test signals Corr1 on pin AUX1

and MinLevel on pin AUX2 . . . . . . . . . . . . . . . . .82

Fig 30. Output ADC channel I on pin AUX1 and

ADC channel Q on pin AUX2. . . . . . . . . . . . . . . .83

Fig 31. Output RxActive on pin AUX1 and

TxActive on pin AUX2 . . . . . . . . . . . . . . . . . . . . .84

Fig 32. Received data stream on pins AUX1 and AUX2 .85

Fig 33. Package outline SOT617-1 (HVQFN32) . . . . . . .86

Fig 34. Packing information 1 tray . . . . . . . . . . . . . . . . . .87

Fig 35. Packing information 5 trays . . . . . . . . . . . . . . . . .88

MFRC523

Contactless reader IC

MFRC523_33

Product data sheet

PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.3 — 5 March 2010

115233

© NXP B.V. 2010. All rights reserved.

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