MIC2184 查看數據表（PDF） - Micrel
零件编号
产品描述 (功能)
生产厂家
MIC2184 Datasheet PDF : 12 Pages
| |||
MIC2184
Micrel, Inc.
Absolute Maximum Ratings (Note 1)
Supply Voltage (VINA, VINP) ......................................... 15V
Digital Supply Voltage (VDD) ........................................... 7V
Comp Pin Voltage (VCOMP) ............................ –0.3V to +3V
Feedback Pin Voltage (VFB) .......................... –0.3V to +3V
Enable Pin Voltage (VEN/UVLO) ..................... –0.3V to 15V
Current Sense Voltage (VCSH–VCSL) ............... –0.3V to 1V
Sync Pin Voltage (VSYNC) ................................ –0.3V to 7V
Freq/2 Pin Voltage (VFREQ/2) ............................ -0.3V to 7V
Power Dissipation (PD)
16 lead SOIC ................................. 400mW @ TA = 85°C
16 lead QSOP ............................... 245mW @ TA = 80°C
Ambient Storage Temp ............................ –65°C to +150°C
ESD Rating, ............................................................. Note 3
Electrical Characteristics
Operating Ratings (Note 2)
Supply Voltage (VINA, VINP) ........................ +2.9V to +14V
Ambient Operating Temperature ......... –40°C ≤ TA ≤ +85°C
Junction Temperature ....................... –40°C ≤ TJ ≤ +125°C
Output Voltage Range ...................................... 1.3V to 12V
PackageThermal Resistance
θJA 16-lead SOP ............................................... 100°C/W
θJA 16-lead QSOP ............................................. 163°C/W
VINA = VINP = VCSH = 5V, VOUT = 3.3V, VEN/UVLO = 5V, VFREQ/2 = 0V, TJ = 25ºC, unless otherwise specified. Bold values indicate
–40ºC < TJ < +125ºC.
Parameter
Condition
Min Typ Max Units
Regulation
Feedback Voltage Reference
(±1%)
1.233 1.245 1.257 V
Feedback Bias Current
(±2%)
1.22
1.27
V
50
nA
Output Voltage Line Regulation
Output Voltage Load Regulation
Output Voltage Total Regulation
Input & VDD Supply
VINA Input Current
VINP Input Current, Note 4
Shutdown Quiescent Current
Digital Supply Voltage (VDD)
Digital Supply load regulation
Undervoltage Lockout
UVLO Hysteresis
5V ≤ VIN ≤ 12V
0mV < (VCSH – VCSL) < 75mV
5V ≤ VINA ≤ 12V, 0mV < (VCSH – VCSL) < 75mV (±3%)
(Excluding external MOSFET gate current)
VEN/UVLO = 0V; (IVINA + IVINP)
IL = 0
IL = 0 to 1mA
VDD upper threshold (turn on threshold)
0.04
%/V
0.9
%
1.208
1.282 V
0.7
mA
1.0
mA
0.5
5
µA
2.82 3.0 3.18
V
0.03
V
2.75
V
100
mV
Reference Output(VREF)
Reference Voltage
(±1.5%)
1.226 1.245 1.264 V
(±2.5%)
1.213
1.276 V
Reference Voltage Line
Regulation
5V < VINA < 12V
2
mV
Reference Voltage Load
Regulation
0 < IREF < 100µA
1
mV
Enable/UVLO
Enable Input Threshold
0.6
0.9
1.2
V
UVLO Threshold
(Turn-on threshold)
1.4
1.5
1.6
V
UVLO Hysteresis
140
mV
Enable Input Current
VEN/UVLO = 5V
0.2
5
µA
M9999-042205
4
April 2005
Share Link: 