MPC9352 查看數據表（PDF） - Motorola => Freescale
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MPC9352 Datasheet PDF : 16 Pages
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Freescale Semiconductor, Inc.
MPC9352
Table 8: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)a
Symbol
Characteristics
Min
Typ
fref
Input reference frequency in PLL modeb ÷4 feedback
50.0
÷6 feedback
33.3
÷8 feedback
25.0
÷12 feedback
16.67
Max
100.0
66.6
50.0
33.3
Unit
MHz
MHz
MHz
MHz
Condition
Input reference frequency in PLL bypass modec
250.0
MHz
fVCO
fMAX
VCO lock frequency ranged
Output Frequency
÷2 outpute
÷4 output
÷6 output
÷8 output
÷12 output
200
100
50
33.3
25
16.67
400
MHz
200
MHz
100
MHz
66.6
MHz
50
MHz
33.3
MHz
frefDC
tr, tf
Reference Input Duty Cycle
CCLK Input Rise/Fall Time
25
75
%
1.0
ns 0.8 to 2.0V
t(∅)
tsk(O)
Propagation Delay CCLK to FB_IN
(static phase offset)
fref > 40 MHz
fref < 40 MHz
Output-to-output Skewf
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
-50
-200
+150
+150
200
200
100
100
ps PLL locked
ps
ps
ps
ps
ps
DC
Output duty cycle
47
50
53
%
tr, tf
Output Rise/Fall Time
0.1
tPLZ, HZ Output Disable Time
tPZL, ZH Output Enable Time
tJIT(CC)
Cycle-to-cycle jitter
output frequencies mixed
outputs are in any ÷4 and ÷6 combination
all outputs same frequency
1.0
ns 0.6 to 1.8V
8
ns
10
ns
400
ps
250
ps
100
ps
tJIT(PER)
Period Jitter
output frequencies mixed
outputs are in any ÷4 and ÷6 combination
all outputs same frequency
200
ps
150
ps
75
ps
tJIT(∅)
BW
I/O Phase Jitter
÷4 feedback divider RMS (1 σ)g
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
PLL closed loop bandwidthh
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
15
20
18 - 20
25
1.0 - 8.0
0.7 - 3.0
0.5 - 2.5
0.4 - 1.0
ps
ps
ps
ps
MHz
MHz
MHz
MHz
tLOCK
Maximum PLL Lock Time
10
ms
a AC characteristics apply for parallel output termination of 50Ω to VTT.
b PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a ÷2 divider for feedback.
c In PLL bypass mode, the MPC9352 divides the input reference clock.
d The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
e See Table 9 and Table 10 for output divider configurations.
f See application section for part-to-part skew calculation.
g See application section for a jitter calculation for other confidence factors than 1 s.
h -3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
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Go to: www.freescale.com
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