MSM6262-XX 查看數據表（PDF） - Oki Electric Industry

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MSM6262-XX

DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER

Oki Electric Industry 

¡ Semiconductor

MSM6262-xx

FUNCTIONAL DESCRIPTION

1. Instruction Register (IR) and Data Register (DR)

The MSM6262-xx has two registers, instruction register (IR) and data register (DR).

IR is used to store the address code or instruction code of display data RAM (DD RAM) or

character generator RAM (CG RAM).

This register can be written by the CPU, but cannot be read out by the CPU.

DR is used to store the data to write into (or read out) the data to/from DD RAM or CG RAM.

The data written into DR by the CPU is automatically written into the DD RAM or CG RAM.

When an address code is written into IR, the data of the specified address is automatically

transferred to the DR from either DD RAM or CG RAM. By having the CPU subsequently read

the DR, it is possible to verify DD RAM or CG RAM data.

After the writing of DR by the CPU, the DD RAM or CG RAM of the next address is selected

to be ready for the next CPU writing.

Likewise, after the reading operation of the CPU, DD RAM or CG RAM data of the next

address is transferred to the DR, when CPU is ready for the next reading operation.

2. Busy Flag (BF)

When the output of BUSY 1 OUT is "H", MSM6262-xx is engaged in internal operation.

When the output of BUSY 2 OUT is "H", it indicates that MSM6262-xx is engaged in internal

operation or MSM6262-xx is engaged in the revising of the display starting line on the LCD.

(Refer to the instruction table.)

When the output of BUSY 1 OUT is "H", any input of new instruction is ignored. So, before

setting a new instruction, it is necessary to check whether BUSY 1 OUT and BUSY 2 OUT are

at "L".

3. Address Counter (ADC)

The address counter (ADC) allocates the address for the DD RAM and CG RAM write/read

and also for the cursor display.

When the instruction code for a DD RAM address or CG RAM address setting is input to IR,

after deciding whether it is DD RAM or CG RAM, the address counter code is transferred from

IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM, the

ADC increments (or decrements) by 1 automatically as its internal operation.

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