MSM6562B 查看數據表（PDF） - Oki Electric Industry
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MSM6562B Datasheet PDF : 50 Pages
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MSM6562B-xx
(2) When the character pattern is 5 ¥ 10 dots (see Table 4).
• Method of writing character pattern into the CG RAM by the CPU :
The CG RAM address bits 0 to 3 correspond to the line position of the character pattern.
First, set increment or decrement by the CPU, and then input the CG RAM address.
After this, write the character pattern into the CG RAM through DB0 to DB7 line by line.
DB0 to DB7 correspond to the CG RAM data bits 0 to 7, in Table 4.
The display of the character pattern is turned on when "H" is set as the input data, while
it is turned off when "L" is set as the input data.
Since the ADC is automatically incremented or decremented by 1 after writing the data
to the CG RAM, it is not necessary to set the CG RAM address again.
When performing a cursor indication, set to "0" all the input data for the line the CG RAM
address bits 0 to 2 are all "1".
CG RAM data is displayed on the LCD when the CG RAM data ranges from CG RAM data
bits 0 to 4 and the CG RAM addresses (address bits 0 to 3) are "0" to "A" (hex.). Other CG
RAM data is not displayed on the LCD (that is, when the CG RAM data ranges from CG
RAM data bits 5 to 7 and the CG RAM addresses (address bits 0 to 3) are "B" to "F" (hex.)).
It is possible, however, to read such CG RAM data through DB0 to DB7.
• Method of displaying the CG RAM character pattern to the LCD :
The CG RAM is selected when high-order 4 bits of the character code are all "L".
Since bits 0 and 3 of the character code are invalid, the display of "b" in Table 4 is selected
by character codes "00", "01", "08" and "09" (hex.).
When the 8-bit character code of the CG RAM character code is written to the DD RAM,the
character pattern of the CG RAM is displayed on the LCD display position corresponding
to the DD RAM address.
(DD RAM data bits 1 to 2 correspond to CG RAM address bits 4 to 5.)
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