MSM66573 查看數據表（PDF） - Oki Electric Industry
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MSM66573 Datasheet PDF : 28 Pages
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1Semiconductor
PEDL66573-02
MSM66573 Family
(2) External data memory control
Parameter
Cycle time
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
RD pulse width
WR pulse width
RD pulse delay time
WR pulse delay time
Address setup time
Address hold time
Read data setup time
Read data hold time
Read data access time
Write data setup time
Write data hold time
Symbol
tcyc
tφWH
tφWL
tRW
tWW
tRD
tWD
tAS
tAH
tRS
tRH
tACC
tWS
tWH
MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Condition
Min.
Max.
Unit
fOSC=30 MHz
33.3
—
13
—
13
—
2tφ–15
—
2tφ–15
—
—
45
CL=50 pF
—
45
ns
tφ–25
—
tφ–3
—
25*1
—
0
—
—
3tφ–65*2
2tφ–30
—
tφ–3
—
Note: t =tcyc/2
*1: MSM66P573=30
*2: MSM66P573=3t –70
CPUCLK
RD
A0 to A19
D0 to D7
WR
A0 to A19
D0 to D7
tcyc
tφWH
tφWL
tRD
tRW
RAP0 to 19
tAS
tAH
DIN0 to 7
tACC
tRS
tRH
tWD
tWW
RAP0 to 19
tAS
tAH
DOUT0 to 7
tWS
tWH
Bus timing during no wait cycle time
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