MSM7717 查看數據表（PDF） - Oki Electric Industry

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MSM7717

Single Rail CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7717-01/02/03

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TIMING DIAGRAM

PCM Data Input/Output Timing

Transmit Timing

BCLK

1234

tXS

tSX

5

6

78

tWSL

9

10

XSYNC

tWSH

tXD1 tSD tXD2

tXD3

PCMOUT

MSD D2 D3 D4 D5 D6 D7 D8

,
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1.

When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD.

Receive Timing

BCLK

tRS

RSYNC

123456789

tSR

tWSH

tWSL

10

tDS

tDH

PCMIN

MSD D2 D3 D4 D5 D6 D7 D8

Figure 1 Basic Timing

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