MT16VDDF12864HY-265 查看數據表（PDF） - Micron Technology
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MT16VDDF12864HY-265 Datasheet PDF : 31 Pages
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512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-26A, -265, -202)
Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS
-26A
-265
-202
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
Access window of DQs from CK/CK#
tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns
CK high-level width
tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
26
CK low-level width
tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
26
Clock cycle time
CL=2.5 tCK (2.5) 7.5 13
7.5
13
8
13
ns 40, 46
CL=2 tCK (2) 7.5 13
10
13 10 13
ns 40, 46
DQ and DM input hold time relative to DQS
tDH 0.5
0.5
0.6
DQ and DM input setup time relative to DQS
tDS
0.5
0.5
0.6
DQ and DM input pulse width (for each input)
tDIPW 1.75
1.75
2
ns 23, 27
ns 23, 27
ns
27
Access window of DQS from CK/CK#
tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns
DQS input high pulse width
tDQSH 0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL 0.35
0.35
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, tDQSQ
0.5
per access
0.5
0.6
ns 22, 23
Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS falling edge to CK rising - setup time
tDSS 0.20
0.20
0.20
tCK
DQS falling edge from CK rising - hold time
tDSH 0.20
0.20
0.20
tCK
Half clock period
tHP
tCH,tCL
tCH,tCL
tCH,tCL
ns
8
Data-out high-impedance window from CK/CK#
tHZ
+0.75
+0.75
+0.8 ns 16, 37
Data-out low-impedance window from CK/CK#
tLZ -0.75
-0.75
-0.8
Address and control input hold time (fast slew
tIHF 0.90
0.90
1.1
rate)
Address and control input setup time (fast slew rate) tISF .900
0.90
1.1
Address and control input hold time (slow slew rate) tIHS
1
1
1.1
Address and control input setup time (slow slew
rate)
tISS
1
1
1.1
ns 16, 38
ns
12
ns
12
ns
12
ns
12
Address and Control input pulse width (for each tIPW 2.2
2.2
2.2
ns
input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
tMRD 15
15
16
ns
tQH
tHP -tQHS
tHP -tQHS
tHP -tQHS
ns
22, 23
Data hold skew factor
tQHS
0.75
0.75
1
ns
ACTIVE to PRECHARGE command
tRAS 40 120,000 40 120,000 40 120,000 ns
31
ACTIVE to READ with Auto precharge command tRAP 20
20
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command
tRC
65
65
70
ns
period
AUTO REFRESH command period
tRFC 75
75
80
ns
44
ACTIVE to READ or WRITE delay
tRCD 20
20
20
ns
PRECHARGE command period
tRP
20
20
20
ns
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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