MT48LC8M32B2 查看數據表（PDF） - Micron Technology
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MT48LC8M32B2 Datasheet PDF : 55 Pages
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A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
PRELIMINARY
256Mb: x32
SDRAM
latency; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until tRP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
T0
CLK
COMMAND
READ
ADDRESS
BANK a,
COL n
Figure 11
READ to PRECHARGE
T1
T2
T3
T4
T5
T6
NOP
NOP
t RP
NOP
PRECHARGE
NOP
NOP
X = 0 cycles
BANK
(a or all)
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
CAS Latency = 1
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t RP
NOP
PRECHARGE
NOP
NOP
X = 1 cycle
BANK
(a or all)
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 2
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
T7
t RP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
X = 2 cycles
ACTIVE
BANK a,
ROW
DQ
CAS Latency = 3
NOTE: DQM is LOW.
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DON’T CARE
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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