MVTX2803 查看數據表（PDF） - Zarlink Semiconductor Inc
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MVTX2803 Datasheet PDF : 127 Pages
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MVTX2803
Data Sheet
2.0 System Configuration
The MVTX2803AG can be configured by EEPROM (24C02 or compatible) via an I2C interface at boot time, or
via a synchronous serial interface during operation.
2.1 I2C Interface
The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL carries the
control signals that facilitate the transfer of information from the EEPROM to the switch. Data transfer is a
bidirectional 8-bit serial at a rate of 50 Kbps. Data transfer is performed between master and slave IC using a
request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data
transfer. The figure below shows the data transfer format.
START
SLAVE
ADDRESS
R/W ACK DATA 1 ACK
(8 bits)
DATA 2
(8 bits)
ACK
DATA M
(8 bits)
Figure 2 - Data Transfer Format for I2C Interface
ACK STOP
2.1.1 Start Condition
Generated by the master, the MVTX2803AG. The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if, while the SCL line is High, there is a High-to-Low transition of the SDA.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus
is free, both lines are High.
2.1.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.1.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.1.4 Acknowledgment
Like all clock pulses, the master generates the acknowledgment-related clock pulse. However, the transmitter
releases the SDA (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the
SDA during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts
the transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line
to let the master generate the Stop condition.
2.1.5 Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB-first.
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