MX7839 查看數據表（PDF） - Maxim Integrated

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MX7839

Octal, 13-Bit Voltage-Output DAC with Parallel Interface

Maxim Integrated 

Octal, 13-Bit Voltage-Output DAC

with Parallel Interface

Table 3. Analog Voltage vs. Digital Code

INPUT CODE

OUTPUT

VOLTAGE (V)

1 1111 1111 1111

+9.997558

1 0000 0000 0000

0

0 1001 1101 1001

-3.845215

0 0000 0000 0001

-9.997558

0 0000 0000 0000

-10

Note: Output voltage is based on REF+ = +5V, REF- = -5V, and

DUTGND = 0V.

Output Voltage Range

For typical operation, connect DUTGND to signal ground,

VREF+ to +5V, and VREF- to -5V. Table 3 shows the rela-

tionship between digital code and output voltage.

The DAC digital code controls each leg of the 13-bit

R-2R ladder. A code of 0x0 connects all legs of the lad-

der to REF-, corresponding to a DAC output voltage

(VDAC) equal to REF-. A code of 0x1FFF connects all

legs of the ladder to REF+, corresponding to a VDAC

approximately equal to REF+.

The output amplifier multiplies VDAC by 2, yielding an out-

put voltage range of 2 ✕ REF- to 2 ✕ REF+ (Figure 1).

Further manipulation of the output voltage span is accom-

plished by offsetting DUTGND. The output voltage of the

MX7839 is described by the following equation:

( ) VOUT =



2 VREF+



−

VREF −

DATA

213

+

VREF −







− VDUTGND

where DATA is the numeric value of the DAC’s binary

input code, and DATA ranges from 0 to 8191

(213 - 1). The resolution of the MX7839, defined as

1 LSB, is described by the following equation:

2(REF+ − REF− )

LSB =

213

Reference Selection

Because the MX7839 has precision buffers on its refer-

ence inputs, the requirements for interfacing to these

inputs are minimal. Select a low-drift, low-noise refer-

ence within the recommended REF+ and REF- voltage

ranges. The MX7839 does not require bypass capaci-

tors on its reference inputs. Add capacitors only if the

reference voltage source requires them to meet system

specifications.

Minimizing Output Glitch

The MX7839’s internal deglitch circuitry is enabled on

the falling edge of LDAC. Therefore, to achieve opti-

mum performance, drive LDAC low after the inputs are

either latched or steady state. This is best accom-

plished by having the falling edge of LDAC occur at

least 50ns after the rising edge of CS.

Power Supplies, Grounding,

and Bypassing

For optimum performance, use a multilayer PC board

with an unbroken analog ground. For normal operation,

connect the four DUTGND pins directly to the ground

plane. Avoid sharing the connections of these sensitive

pins with other ground traces.

As with any sensitive data-acquisition system, connect

the digital and analog ground planes together at a sin-

gle point, preferably directly underneath the MX7839.

Avoid routing digital signals underneath the MX7839 to

minimize their coupling into the IC.

For normal operation, bypass VDD and VSS with 0.1µF

ceramic chip capacitors to the analog ground plane. To

enhance transient response and capacitive drive capa-

bility, add 10µF tantalum capacitors in parallel with the

ceramic capacitors. Note, however, that the MX7839

does not require the additional capacitance for stability.

Bypass VCC with a 0.1µF ceramic chip capacitor to the

digital ground plane.

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