NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 29. Page Read A/ Read B Operation AC Waveform
CL
tEHEL
E
tWLWL
W
tEHQZ
tWHBL
AL
tEHBH
tWHBH
tALLRL2
tRLRL
(Read Cycle time)
tRHQZ
R
tBLBH1
tRLRH
tRHBL
RB
I/O
00h or Add.N Add.N Add.N Add.N
01h cycle 1 cycle 2 cycle 3 cycle 4
Data
N
Data Data
N+1 N+2
Data
Last
Command
Code
Address N Input
Data Output
Busy from Address N to Last Byte or Word in Page
Note: Address cycle 4 is only required for 512Mb and 1Gb devices.
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