NCP1207A(2004) 查看數據表（PDF） - ON Semiconductor

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NCP1207A
(Rev.:2004)

PWM Current-Mode Controller for Free Running Quasi-Resonant Operation

ON Semiconductor 

NCP1207A

Calculating the Vcc Capacitor

As the above section describes, the fall down sequence

depends upon the VCC level: how long does it take for the

VCC line to go from 12 V to 10 V? The required time depends

on the startup sequence of your system, i.e. when you first

apply the power to the IC. The corresponding transient fault

duration due to the output capacitor charging must be less

than the time needed to discharge from 12 V to 10 V,

otherwise the supply will not properly start. The test consists

in either simulating or measuring in the lab how much time

the system takes to reach the regulation at full load. Let’s

suppose that this time corresponds to 6.0 ms. Therefore a

VCC fall time of 10 ms could be well appropriated in order

to not trigger the overload detection circuitry. If the

corresponding IC consumption, including the MOSFET

drive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET),

we can calculate the required capacitor using the following

formula:

Dt

+

DV @

i

C,

with

DV

=

2.0

V.

Then

for

a

wanted

Dt of 10 ms, C equals 9.0 mF or 22 mF for a standard value.

When an overload condition occurs, the IC blocks its

internal circuitry and its consumption drops to 330 mA

typical. This happens at VCC = 10 V and it remains stuck

until VCC reaches 5.3 V: we are in latchoff phase. Again,

using the calculated 22 mF and 330 mA current consumption,

this latchoff phase lasts: 313 ms.

HV Pin Recommended Protection

When the user unplugs a power supply built with a QR

controller such as the NCP1207A, one instance can occur:

A negative ringing can take place on pin8 due to a

resonance between the primary inductance and the bulk

capacitor. As any CMOS device, the NCP1207A is sensitive

to negative voltages that could appear on it’s pins and could

create an internal latch−up condition.

For this reason, we recommend adding a resistor between

the bulk capacitor and the VCC pin.

Operation Shots

Below are some oscilloscope shots captured at

Vin = 120 VDC with a transformer featuring a 800 mH

primary inductance.

Figure 25.

This plot gathers waveforms captured at three different

operating points:

1st upper plot: free run, valley switching operation,

Pout = 26 W

2nd middle plot: min Toff clamps the switching frequency

and selects the second valley

3rd lowest plot: the skip slices the second valley pattern

and will further expand the burst as Pout goes low

VGATE (5 V/div)

VRsense (200 mV/div)

200 mA X RSKIP

Current Sense Pin (200 mV/div)

Figure 26.

This picture explains how the 200 mA internal offset

current creates the skip cycle level.

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