NCP3020A 查看數據表（PDF） - ON Semiconductor

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NCP3020A

Synchronous PWM Controller

ON Semiconductor 

NCP3020A, NCP3020B, NCV3020A, NCV3020B

CURRENT LIMIT AND CURRENT LIMIT SET

Overview

The NCP3020 uses the voltage drop across the High Side

MOSFET during the on time to sense inductor current. The

ILimit block consists of a voltage comparator circuit which

compares the differential voltage across the VCC Pin and the

VSW Pin with a resistor settable voltage reference. The sense

portion of the circuit is only active while the HS MOSFET

is turned ON.

VIN

VCC

Ilim Out

CONTROL

6

DAC /

COUNTER

VSense

Itrip Ref

Switch

Cap

HSDR

VSW

Iset

13 uA

Vset

LSDR

RSet

Itrip Ref−63 Steps, 6.51 mV/step

Figure 26. Iset / ILimit Block Diagram

Current Limit Set

The ILimit comparator reference is set during the startup

sequence by forcing a typically 13 mA current through the

low side gate drive resistor. The gate drive output will rise

to a voltage level shown in the equation below:

Vset + Iset * Rset

(eq. 1)

Where ISET is 13 mA and RSET is the gate to source resistor

on the low side MOSFET.

This resistor is normally installed to prevent MOSFET

leakage from causing unwanted turn on of the low side

MOSFET. In this case, the resistor is also used to set the

ILimit trip level reference through the ILimit DAC. The Iset

process takes approximately 350 ms to complete prior to

Soft−Start stepping. The scaled voltage level across the ISET

resistor is converted to a 6 bit digital value and stored as the

trip value. The binary ILimit value is scaled and converted to

the analog ILimit reference voltage through a DAC counter.

The DAC has 63 steps in 6.51 mV increments equating to a

maximum sense voltage of 403 mV. During the Iset period

prior to Soft−Start, the DAC counter increments the

reference on the ISET comparator until it crosses the VSET

voltage and holds the DAC reference output to that count

value. This voltage is translated to the ILimit comparator

during the ISense portion of the switching cycle through the

switch cap circuit. See Figure 26. Exceeding the maximum

sense voltage results in no current limit. Steps 0 to 10 result

in an effective current limit of 0 mV.

Current Sense Cycle

Figure 27 shows how the current is sampled as it relates

to the switching cycle. Current level 1 in Figure 27

represents a condition that will not cause a fault. Current

level 2 represents a condition that will cause a fault. The

sense circuit is allowed to operate below the 3/4 point of a

given switching cycle. A given switching cycle’s 3/4 Ton

time is defined by the prior cycle’s Ton and is quantized in

10 ns steps. A fault occurs if the sensed MOSFET voltage

exceeds the DAC reference within the 3/4 time window of

the switching cycle.

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