NCV7361A(2004) 查看數據表（PDF） - ON Semiconductor

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NCV7361A
(Rev.:2004)

Voltage Regulator with Integrated LIN Transceiver

ON Semiconductor 

NCV7361A

VBUS

MIN/MAX SLOPE TIME CALCULATION

100%

95%

BUS

40%

0%

tsdom

60%

Vdom

5%

tsrec

Figure 27. Slope Time Calculation

The slew rate of the bus voltage is measured between

40% and 60% of the output voltage swing (linear region).

The output voltage swing is the difference between

dominant and recessive bus voltage.

dVńdt + 0.2 * Vswingń(t40%−t60%)

The slope time is the extension of the slew rate tangent

until the upper and lower voltage swing limits:

tslope + 5 * (t40%−t60%)

The slope time of the recessive to dominant edge is directly

determined by the slew rate control of the transmitter:

tslope + VswingńdVńdt

The dominant to recessive edge is influenced from the

network time constant and the slew rate control, because

it’s a passive edge. In case of low battery voltages and high

bus loads the rising edge is only determined by the network.

If the rising edge slew rate exceeds the value of the

dominant one, the slew rate control determines the rising

edge.

Power Dissipation and Operating Range

The max power dissipation depends on the thermal

resistance of the package and the PCB, the temperature

difference between Junction and Ambient as well as the

airflow.

The power dissipation can be calculated with:

PD + (VSUP * VOUT) * IVOUT ) PD_TX

The power dissipation of the transmitter PD_TX depends

on the transceiver configuration and its parameters as well

as on the bus voltage VBUS = VBAT − VD, the resulting

termination resistance RL, the capacitive bus load CL and

the bit rate. Figure 28 shows the dependence of power

dissipation of the transmitter as function of VSUP. The

conditions for calculation the power dissipation was:

RL = 500 W, CL = 10 nF, Bitrate = 20 kbit and duty cycle

on TxD of 50%.

50

45

40

35

30

25

20

15

10

5

0

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

VSUP (V)

Figure 28. Power Dissipation LIN Transceiver

@ 20 kbit

The permitted package power dissipation can be

calculated:

PDmax

+

TJ * TA

RqJ−A

If we consider that PD_TX_max = f(VSUP), it can be

calculated the max output current IVOUT on VOUT:

IVOUTmax

+

TJ−TA

RqJ−A

* PD_TX_max @

VSUP * VOUT

VSUP

TJ−TA is the temperature difference between junction

and ambient, and Rth is the thermal resistance of the

package. The thermal energy is transferred via the package

and the pins to the ambient. This transfer can be improved

with additional ground areas on the PCB as well as ground

areas under the IC.

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