AD7472BRU(2000) 查看數據表（PDF） - Analog Devices

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AD7472BRU
(Rev.:2000)

1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs

Analog Devices 

AD7470/AD7472

0.1␮F

VIN

AD780

VOUT

+

10␮F

AVDD

DVDD

1nF

AGND

DGND AD7470/

AD7472

+

VDRIVE

1nF 10␮F

0.1␮F

+

47␮F

ANALOG

SUPPLY

+5V

+

10␮F 0.1␮F

VREF

Figure 25. Decoupling Circuit

GROUNDING AND LAYOUT

The analog and digital power supplies are independent and

separately pinned out to minimize coupling between analog and

digital sections within the device. To complement the excellent

noise performance of the AD7470/AD7472 it is imperative that

care be given to the PCB layout. Figure 25 shows a recom-

mended connection diagram for the AD7470/AD7472.

All of the AD7470/AD7472 ground pins should be soldered

directly to a ground plane to minimize series inductance. The

AVDD, DVDD and VDRIVE pins should be decoupled to both the

analog and digital ground planes. The large value capacitors will

decouple low frequency noise to analog ground, the small value

capacitors will decouple high frequency noise to digital ground.

All digital circuitry power pins should be decoupled to the digi-

tal ground plane. The use of ground planes can physically sepa-

rate sensitive analog components from the noisy digital system.

The two ground planes should be joined in only one place and

should not overlap so as to minimize capacitive coupling be-

tween them. If the AD7470/AD7472 is in a system where

multiple devices require AGND to DGND connections, the

connection should still be made at one point only, a star ground

point, which should be established as close as possible to the

AD7470/AD7472.

Noise can be minimized by applying some simple rules to the

PCB layout: analog signals should be kept away from digital

signals; fast switching signals like clocks should be shielded with

digital ground to avoid radiating noise to other sections of the

board and clock signals should never be run near the analog

inputs; avoid running digital lines under the device as these will

couple noise onto the die; the power supply lines to the AD7470/

AD7472 should use as large a trace as possible to provide a low

impedance path and reduce the effects of glitches on the power

supply line; avoid crossover of digital and analog signals and

place traces that are on opposite sides of the board at right angles

to each other.

Noise to the analog power line can be further reduced by use of

multiple decoupling capacitors as shown in Figure 25. Decou-

pling capacitors should be placed directly at the power inlet to

the PCB and also as close as possible to the power pins of the

AD7470/AD7472. The same decoupling method should be

used on other ICs on the PCB, with the capacitor leads as short

as possible to minimize lead inductance.

POWER SUPPLIES

Separate power supplies for AVDD and DVDD are desirable but if

necessary DVDD may share its power connection to AVDD. The

digital supply (DVDD) must not exceed the analog supply (AVDD)

by more than 0.3 V in normal operation.

MICROPROCESSOR INTERFACING

AD7470/AD7472 to ADSP-2185 Interface

Figure 26 shows a typical interface between the AD7470/AD7472

and the ADSP-2185. The ADSP-2185 processor can be used in

one of two memory modes, Full Memory Mode and Host Mode.

The Mode C pin determines in which mode the processor works.

The interface in Figure 26 is set up to have the processor work-

ing in Full Memory Mode, which allows full external addressing

capabilities.

When the AD7470/AD7472 has finished converting, the BUSY

line requests an interrupt through the IRQ2 pin. The IRQ2

interrupt has to be set up in the interrupt control register as

edge-sensitive. The DMS (Data Memory Select) pin latches in

the address of the A/D into the address decoder. The read op-

eration is thus started.

OPTIONAL

A0–A15

ADSP-2185*

DMS

ADDRESS BUS

ADDRESS

DECODER

IRQ2

RD

100k⍀

MODE C

D0–D23

DATA BUS

CONVST

AD7470/

AD7472*

CS

BUSY

RD

DB0–DB9

(DB11)

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 26. Interfacing to the ADSP-2185

AD7470/AD7472 to ADSP-21065 Interface

Figure 27 shows a typical interface between the AD7470/AD7472

and the ADSP-21065L SHARC® processor. This interface is an

example of one of three DMA handshake modes. The MSX

SHARC is a registered trademark of Analog Devices, Inc.

–14–

REV. A

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